Hi,I'm going through "Learning VHDL by example" and the author is using statements like: c <= a AND b after 10 ns; and also... wait for 10 ns; Now when I actually program this in VHDL and then compile and simulate the code in Quartus, these time delays don't show up at my output waveform... Why? What is the statement "AFTER 10ns" actually doing? How does the FPGA know how long 10ns is and why isn't my simulator simulating it? Also why would the author write that in the book if it doesn't actually do anything in real life? I wish the author would explain it better. Thank you!
wait for and after are only for behavioral modeling. They do not translate / map into any physical circuits.
Those statements are ignored by the synthesizer, because as waiyung says they can't be mapped to real hardware. AFAIK the Quartus simulator simulates the output of the synthesizer and not the original code, so it will ignore it too.You can use Modelsim if you want to have a full featured VHDL simulator.
All true, but the most important thing to point out is that theese assignement are usefull only for simulation parpouse.If you need to make a delay, your logic shall implement a counter that trig the event. Since you told that you're a beginner, you've to understand that VHDL in all syntesis tools is a way in which you are describing something that IS BEING IMPLEMENTED. So try to keep in mind always what are implementing how will be done in terms of flip flop and logics blocks. Good learning 🙂