I am trying to get my head around FPGAs and in particular how i could accelerate a C/C++ programs by having some calls have an FPGA compute results.
Ideally, i would want to have some kind of shared memory space whereby an in-memory data structure in C/C++ is accessible via FPGA logic and vice-versa, where some resulting logic is accessible by the C/C++ program -- all the while communication between the CPU based C++ program and the FPGA card is high speed -- essentially via memory access bandwidth.
Can this be done?
IS there some tutorial about this that i could review?
You're basically describing OpenCL or HLS (high-level synthesis). I'm not an expert in either, but check them out.
There are also dedicated FPGA acceleration cards.
Thank you for your response.
I am surely going to deep dive into OpenCL to figure out what can be done with it ...
From what I read, and if i understood this correctly, it seems that OpenCL is an alternative to hardware description languages such as Verilog. Encoded OpenCL calls are implemented in FPGA, while appearing to the developer as specialized C/C++ library functions.
I guess, I had a different kind of "architecture" in mind -- a way to to create an own FPGA "circuit" -- using, for example, Verilog, and then to have a way to memory map the FPGA to a CPU memory on a standard PC.
Perhaps those acceleration cards are close to what i had in mind ...
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