Nios Open Source Alternatives?

[Altera_Forum]

Hi Guys, 

 Being but a Hobbyist i want to build an independant design that does not require hardware tethering. Now all my training is in Altera and i've have some Altera products; which due to this evaluation i'm starting to regret. (I have a terasic TPAD, additional D5M camera, LTM touch screen and a DE0Nano)   is there any open-source cpus out there that people have used? The key thing i'm after is ease of setup, implentation and programming. 

• What disadvantages are there? 
• How is it programmed, IE access JTAG? 
• Can it be debugged? 

   Anticipated trade offs: 

• Would have to abandon the Avalon fabric, perhaps for wishbone? 
• I imagine a Nios2 is probably a more powerful/effcient processor. 

  Does the Xilinx equivalent have the same disadvatage for the hobbyist; it seems that many more projects use Xilinx instead of Altera, is this why?  Thanks in advance guys

[Altera_Forum]

What is wrong with NIOS II/e (economy)? It is free ... 

 http://www.altera.com/devices/processor/nios2/cores/economy/ni2-economy-core.html  OpenCores OpenRISC would probably be the next core I would look at ...  There's also an FPGA-based Arduino board I saw recently that uses an AVR core  http://papilio.cc/  That core is also from OpenCores.  I've not used these cores, so cannot provide positive or negative feedback.  Cheers, Dave

[Altera_Forum]

Awesome Dave, thanks. I had no idea that version of the Nios is free. 

I'll also look into the papillo stuff, but i want to try and use the hardware i've got.  If anyoneelse has any opinions or experiences i'd still love to hear about them.

[Altera_Forum]

--- Quote Start ---  Awesome Dave, thanks. I had no idea that version of the Nios is free. I'll also look into the papillo stuff, but i want to try and use the hardware i've got.  If anyoneelse has any opinions or experiences i'd still love to hear about them.  --- Quote End ---    one of the guys I work with keeps telling me, "just get rid of the CPU and do it all in verilog, its easy!".   I'm beginning to think he is right. We have a large system that consumes around 50K ALMs and has a DDR3 controller, a TSE core, and a bunch of custom logic. And we have recently gone to a pure verilog implentation and removed the CPU by creating our own avalon bus masters and stream/sink objects.   good luck!

[Altera_Forum]

--- Quote Start ---  one of the guys I work with keeps telling me, "just get rid of the CPU and do it all in verilog, its easy!".    --- Quote End ---    That is a topic for a different thread :)  Personally though, I have yet to find a problem I could solve with a soft-core processor, and have never used one in a design. My processor requirements have always exceeded what you can do with an FPGA processor for the price. A 500MHz PowerPC is less than $50, and ARM processors are even cheaper. The newer SoC devices are very interesting though ...  Cheers, Dave

[Altera_Forum]

--- Quote Start ---   And we have recently gone to a pure verilog implentation and removed the CPU by creating our own avalon bus masters and stream/sink objects.    --- Quote End ---    Woah, that i would love top see, hadn't thought that would be an effective option? What can you tell or show me about this?

[Altera_Forum]

I'm not sure I'd want to run Linux on the nios - far too slow. 

But it you have something that has to be done every (say) 100 clocks and has some complex conditionals then the cpu variant will be easier to write and probably use less logic overall. I guess the real trick is to use a mixture of both.  There are also things like TCP connection processing that you won't really manage completely in vhdl (UDP probably can be done in vhdl). OTOH I suspect there are much smaller TCP implementations than the usual lurking culprits - I'd start with something from the early 1980s and cut out the unwanted bits!