Not able to program Agilex FPGA

[Shubhall]

Hi,

I am currently working on Agilex FPGA (Agilex: AGFB014R24B2E2V). I am trying to program it for the generated JESD204B example design (preset 888). While doing same I am getting the error. I have referred this solution (https://community.intel.com/t5/Intel-Quartus-Prime-Software/Error-when-programming-Agilex/td-p/1350037) but nothing seems to work. Kindly help.

Please let me know if more info required from my side.

Note - I am able to generate .sof file successfully.  Quartus version 22.2. 

My VID settings 

set_global_assignment -name USE_PWRMGT_SCL SDM_IO0
set_global_assignment -name USE_PWRMGT_SDA SDM_IO12
set_global_assignment -name VID_OPERATION_MODE "PMBUS MASTER"
set_global_assignment -name PWRMGT_BUS_SPEED_MODE "400 KHZ"
set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE OTHER
set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 42
set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 43
set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 44
set_global_assignment -name PWRMGT_SLAVE_DEVICE3_ADDRESS 00
set_global_assignment -name PWRMGT_SLAVE_DEVICE4_ADDRESS 00
set_global_assignment -name PWRMGT_SLAVE_DEVICE5_ADDRESS 00
set_global_assignment -name PWRMGT_SLAVE_DEVICE6_ADDRESS 00
set_global_assignment -name PWRMGT_SLAVE_DEVICE7_ADDRESS 00
set_global_assignment -name PWRMGT_PAGE_COMMAND_ENABLE ON
set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "LINEAR FORMAT"
set_global_assignment -name PWRMGT_LINEAR_FORMAT_N "-12"

Thank you

Shubh

[ZH_Intel]

Hi Shubhall,

Thank you for reaching out.

Just to let you know that Intel has received your support request and currently we are confirming the details with our internal team.

Allow me some time to look into your issue. I shall come back to you with findings.

Thank you for your patience.

Best Regards,

ZulsyafiqH_Intel

[ZH_Intel]

Hi Shubhall,

Thank you for your patience.

We could not replicate your error on our side and currently I am running some test to replicate it.

I would like to clarify some items below:

Q1. Could you share with us the steps on how you generate the example design? 

    Did you follow the steps as per user guide (Link:F-Tile JESD204B Intel® FPGA IP User Guide - 3.6.2. Parameterizing and Generating the IP )

Q2. May I know the JESD204B configuration that you are using?

Thank you.

Best Regards,

ZulsyafiqH_Intel

[ZH_Intel]

Hi Shubhangi,

Good day.

After further checking it seems like it might be some issue with the VID settings.

Based on your Agilex part number, I believe you are using the Agilex F-Series FPGA devkit Production-2V.

For the VID setting, you are required to input below script/code to avoid Quartus from generating an error due to incomplete SmartVID settings.

Intel® Agilex™ F-Series FPGA Devkit User Guide

You may change the scripts listed below in you project QSF file.

Please ensure that there are no other similar settings with different values.

6.1. Add SmartVID settings in the QSF file

For more information you may refer to below link:

Intel® Agilex™ F-Series FPGA Development Kit User Guide - 6.1. Add SmartVID settings in the QSF file 

Please try this step and let me know if error still happen.

Thank you.

Best Regards,

ZulsyafiqH_Intel

[Shubhall · Accepted solution]

Hi, 

I am sorry for replying late.

Yes this new settings works fine.

Thank you so much for the help.

Regards

Shubhangi

[ZH_Intel]

Hi Shubhangi,

I’m glad that your question has been addressed, I now transition this thread to community support. 

If you have a new question, feel free to open a new thread to get the support from Intel experts. 

Otherwise, the community users will continue to help you on this thread. 

Thank you.

Best Regards,

ZulsyafiqH_Intel