Programmable Devices
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PLL clock output for SDRAM is not connected

william7
Beginner
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I'm mapping my VHDL design to Cyclone IV device. The SDRAM clock is derived from altpll's 2nd clock output. The compilation generates a warning message:

Warning (15899): PLL "clkgen:clkgen0|cyclone_clkgen:\c4:cyc0|cyclonepll:sdclkpll|altpll:\nosd:altpll0|altpll_3p21:auto_generated|pll1" has parameters clk1_multiply_by and clk1_divide_by specified but port CLK[1] is not connected

I check the design to make sure the CLK[1] is surely connected to the output by the following mapping:

sdclk_pad : outpad generic map (2) port map (sdclkl, sdclk);
 
However, sdclk output is broken when looking into the RTL view:
william7_0-1674536605585.png

And the output pin is connected to invalid 

william7_1-1674536850617.png

How could I fix this mapping problem?

Thanks

 

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Farabi
Employee
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Hello,


To debug this, we need a sample case from you. Could you please send us the sample case so we can take a look into this?


regards,

Farabi


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AqidAyman_Intel
Employee
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As we do not receive any response from you on the previous question/reply/answer that we have provided, please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


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