I'm mapping my VHDL design to Cyclone IV device. The SDRAM clock is derived from altpll's 2nd clock output. The compilation generates a warning message:
Warning (15899): PLL "clkgen:clkgen0|cyclone_clkgen:\c4:cyc0|cyclonepll:sdclkpll|altpll:\nosd:altpll0|altpll_3p21:auto_generated|pll1" has parameters clk1_multiply_by and clk1_divide_by specified but port CLK is not connected
I check the design to make sure the CLK is surely connected to the output by the following mapping:
And the output pin is connected to invalid
How could I fix this mapping problem?