Output HSMC pin via Ethernet port on DE10 Standard FPGA

[greenlantern01]

Hello,

I am currently working on a DE10 Standard FPGA along with a DC2390 Daughter Card. I want to get the ADC output from the daughter card (HSMC) and output it via the Ethernet port on the DE10.

Are there any reference designs which show FPGA to HPS interfacing on Platform Designer?

Any help is greatly appreciated!

Thank you & Regards

[JingyangTeh]

Hi

You could get the reference material for the DE10 Standard from the Terasic website below:

https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=165&No=1081&PartNo=4#contents

In the Quartus project you could see the enablement of the HPS in the Platform Designer Tool.

Regards

Jingyang, Teh

[greenlantern01]

Hi Jingyang,

Thanks for your response!

I have gone through those reference designs. They do provide some information on HSMC and daughter cards. I was wondering if there was anything that would help with in building a Platform Designer system to output the data from the ethernet, either via HPS or FPGA? 

Kindly let me know.

Thank you & Regards

[JingyangTeh]

Hi

Sorry I am not very clear what you are looking for.

Are you looking for an example design for the HPS Ethernet Peripheral?

For the HPS Ethernet, if you would like to connect it to other pins you could do it by routing it through the fpga instead of the HPS dedicated IO pins.

You could take a look at the platform designer user guide below if you are unsure on the platform designer environment:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/archives/ug-qpp-platform-designer-19-1.pdf

Regards

Jingyang, Teh

[greenlantern01]

Hi Jingyang,

Yes. I am looking for an example design that I could refer to, to transmit the data from the HSMC port on the FPGA  to the ethernet port which is connected to the HPS.

I am currently using DE10 Standard Development Kit (Cyclone V SoC) along with DC2390 Daughter card.

Thank you & Regards

[JingyangTeh]

Hi

Sorry there is no HSMC example design for the HSMC pins.

However I found some user guide stating some example design from the DC2390A-A board that you are using.

https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/dc2390a-a.html#eb-overview

Regards

Jingyang, Teh

[JingyangTeh]

Hi

Do you have any more follow up question for this case?

Regards

Jingyang, Teh

[greenlantern01]

Yes, I was able to find some other reference designs to help me with this. I was wondering if it is possible to use the Triple Speed Ethernet Intel FPGA IP with Cyclone V SoC on DE10 Standard FPGA? Kindly share the reference design if available. 

Thank you.

[JingyangTeh]

Hi

Yes. The triple speed ethernet IP is supported for CycloneV

https://www.intel.com/content/www/us/en/docs/programmable/683402/22-4-21-1-0/device-family-support.html

Regards

Jingyang, Teh

[JingyangTeh]

Hi

Any more follow up question for this case?

Regards

Jingyang, Teh

[greenlantern01]

Can I use the below SPI core IP with HPS instead of Nios II? 

5. SPI Core (intel.com)

[JingyangTeh]

Hi

Yes you may use the SPI with HPS.

In general you will need to add the SPI node in the device tree with the required linux driver and it will appear in the linux device.

Refer below for the linux driver used for the SPI device.

https://www.rocketboards.org/foswiki/Documentation/LinuxDrivers

Regards

Jingyang, Teh

[greenlantern01]

Excellent! That link was extremely helpful! 

I am currently trying to compile my project. I've used the Triple Speed Ethernet IP. However, this error shows up when compiling.

Error (15871): Input port DATAIN of DDIO_IN primitive "hps_ethernet:u0|hps_ethernet_Ethernet:ethernet|altera_eth_tse_mac:i_tse_mac|altera_tse_rgmii_module:U_RGMII|altera_tse_rgmii_in1:the_rgmii_in1|altddio_in:altddio_in_component|ddio_in_gsd:auto_generated|ddio_ina[0]" must come from an I/O IBUF or DELAY_CHAIN primitive

Could you provide some guidance on how to solve this?

Thank you!

[JingyangTeh]

Hi

When generating the Triple-Speed Ethernet IP Core IP with RGMII, the TSE IP Core already has ALTDDIO megafunctions inside. rgmii_in[3:0], rx_control, rgmii_out[3:0], and tx_control ports of the TSE IP Core are supposed to be mapped to I/O IBUF, thus additional ALTDDIO_IN megafuction shouldn't be inserted between I/O IBUF and the TSE IP Core.

Regards

Jingyang, Teh

[greenlantern01]

I somehow managed to get that error solved. 

The design is now finally ready. I was trying to figure ways to test it. Is it possible to test this design via eclipse. I saw tutorials for testing the design using eclipse if nios 2 processor is used. But couldn't find any which use HPS.

Also is it possible to debug the design using signaltap? 

Can you suggest some ways? 

Thanks 

[JingyangTeh]

Hi

Yeah you could either use Signal Tap or Eclipse to debug.

You could refer below link on the tool usage.

Signal Tap:

https://www.intel.com/content/www/us/en/docs/programmable/683819/23-4/step-1-add-the-logic-analyzer-to-the-project.html

Eclipse Tool:

https://www.rocketboards.org/foswiki/Documentation/LinuxApplicationDebuggingWithDS5

Regards

Jingyang, Teh

[greenlantern01]

Hi,

The example that you shared for Eclipse Tool was for debugging Linux Applications. Are the any examples which show eclipse being used for debugging HPS? Are there any other ways to just simulate the Qsys design?

Thanks

[JingyangTeh]

Hi

The debug tool will be debugging the linux application in HPS.

Are you trying to debug the linux OS?

You are able to simulate some softIP from quartus.

Regards

Jingyang, Teh

[JingyangTeh]

Hi

Since there are no feedback for this thread, I shall set this thread to close pending. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

If you happened to close this thread you might receive a survey. If you think you would rank your support experience less than 4 out of 10, please allow me to correct it before closing or if the problem can’t be corrected, please let me know the cause so that I may improve your future service experience.

Regards

Jingyang, Teh