Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
21145 Discussions

PCIe hip transceiver toolkit not detected

SSilu
Beginner
1,254 Views

I'm receiving following errors when try to run transceiver toolkit for Arria 10 pcie hip.

mar 02, 2020 9:16:38 AM com.altera.debug.core INFO: Created link from (link)/JTAG/alt_sld_fab_0_alt_sld_fab_0_sldfabric.node_0/alt_sld_fab_0_alt_sld_fab_0_host_link_jtag.h2t/alt_sld_fab_0_alt_sld_fab_0_stfabric.h2t_1/alt_sld_fab_0_alt_sld_fab_0_memfabric_1_transacto.avalon_master/slave_28000 to (files)/sdnbox_pcb_tester.sof/sdnbox_pcb_tester.sld/master_21_0.slave   mar 02, 2020 9:16:43 AM com.altera.debug.core SEVERE: TTK failed reading from PHY slave_28000, cannot enable TTK functionality for this PHY. Please verify the reconfig_clk is running and ensure this PHY is not stuck in reset.   mar 02, 2020 9:17:39 AM com.altera.debug.core WARNING: Couldn't grab settings for channel TX|1|phy_8000|pcie_gen.pcie_avmm_dma_inst|pcie_a10_hip_0|7   mar 02, 2020 9:17:44 AM com.altera.debug.core WARNING: Couldn't grab settings for channel TX|1|phy_8000|pcie_gen.pcie_avmm_dma_inst|pcie_a10_hip_0|6   mar 02, 2020 9:17:49 AM com.altera.debug.core WARNING: Couldn't grab settings for channel TX|1|phy_8000|pcie_gen.pcie_avmm_dma_inst|pcie_a10_hip_0|5   mar 02, 2020 9:17:54 AM com.altera.debug.core WARNING: Couldn't grab settings for channel TX|1|phy_8000|pcie_gen.pcie_avmm_dma_inst|pcie_a10_hip_0|4   mar 02, 2020 9:17:59 AM com.altera.debug.core WARNING: Couldn't grab settings for channel TX|1|phy_8000|pcie_gen.pcie_avmm_dma_inst|pcie_a10_hip_0|3   mar 02, 2020 9:18:04 AM com.altera.debug.core WARNING: Couldn't grab settings for channel TX|1|phy_8000|pcie_gen.pcie_avmm_dma_inst|pcie_a10_hip_0|2   mar 02, 2020 9:18:09 AM com.altera.debug.core WARNING: Couldn't grab settings for channel TX|1|phy_8000|pcie_gen.pcie_avmm_dma_inst|pcie_a10_hip_0|1   mar 02, 2020 9:18:14 AM com.altera.debug.core WARNING: Couldn't grab settings for channel TX|1|phy_8000|pcie_gen.pcie_avmm_dma_inst|pcie_a10_hip_0|0   mar 02, 2020 9:18:19 AM com.altera.debug.core WARNING: Couldn't grab settings for channel RX|1|phy_8000|pcie_gen.pcie_avmm_dma_inst|pcie_a10_hip_0|7   mar 02, 2020 9:18:24 AM com.altera.debug.core WARNING: Couldn't grab settings for channel RX|1|phy_8000|pcie_gen.pcie_avmm_dma_inst|pcie_a10_hip_0|6   mar 02, 2020 9:18:29 AM com.altera.debug.core WARNING: Couldn't grab settings for channel RX|1|phy_8000|pcie_gen.pcie_avmm_dma_inst|pcie_a10_hip_0|5   mar 02, 2020 9:18:34 AM com.altera.debug.core WARNING: Couldn't grab settings for channel RX|1|phy_8000|pcie_gen.pcie_avmm_dma_inst|pcie_a10_hip_0|4   mar 02, 2020 9:18:39 AM com.altera.debug.core WARNING: Couldn't grab settings for channel RX|1|phy_8000|pcie_gen.pcie_avmm_dma_inst|pcie_a10_hip_0|3   mar 02, 2020 9:18:44 AM com.altera.debug.core WARNING: Couldn't grab settings for channel RX|1|phy_8000|pcie_gen.pcie_avmm_dma_inst|pcie_a10_hip_0|2   mar 02, 2020 9:18:49 AM com.altera.debug.core WARNING: Couldn't grab settings for channel RX|1|phy_8000|pcie_gen.pcie_avmm_dma_inst|pcie_a10_hip_0|1   mar 02, 2020 9:18:54 AM com.altera.debug.core WARNING: Couldn't grab settings for channel RX|1|phy_8000|pcie_gen.pcie_avmm_dma_inst|pcie_a10_hip_0|0   mar 02, 2020 9:18:59 AM com.altera.debug.core WARNING: Could not determine current equalizer.   mar 02, 2020 9:19:04 AM com.altera.debug.core WARNING: Could not determine current equalizer.   mar 02, 2020 9:19:10 AM com.altera.debug.core WARNING: Could not determine current equalizer.   mar 02, 2020 9:19:15 AM com.altera.debug.core WARNING: Could not determine current equalizer.   mar 02, 2020 9:19:20 AM com.altera.debug.core WARNING: Could not determine current equalizer.   mar 02, 2020 9:19:25 AM com.altera.debug.core WARNING: Couldn't grab settings for channel LINK|1|slave_8000|pcie_gen.pcie_avmm_dma_inst|pcie_a10_hip_0|7   mar 02, 2020 9:19:30 AM com.altera.debug.core WARNING: Could not determine current equalizer.   mar 02, 2020 9:19:35 AM com.altera.debug.core WARNING: Could not determine current equalizer.   mar 02, 2020 9:19:40 AM com.altera.debug.core WARNING: Could not determine current equalizer.   mar 02, 2020 9:19:45 AM com.altera.debug.core WARNING: Could not determine current equalizer.   mar 02, 2020 9:19:50 AM com.altera.debug.core WARNING: Could not determine current equalizer.   mar 02, 2020 9:19:55 AM com.altera.debug.core WARNING: Couldn't grab settings for channel LINK|1|slave_8000|pcie_gen.pcie_avmm_dma_inst|pcie_a10_hip_0|6   mar 02, 2020 9:20:00 AM com.altera.debug.core WARNING: Could not determine current equalizer.   mar 02, 2020 9:20:05 AM com.altera.debug.core WARNING: Could not determine current equalizer.   mar 02, 2020 9:20:10 AM com.altera.debug.core WARNING: Could not determine current equalizer.   mar 02, 2020 9:20:15 AM com.altera.debug.core WARNING: Could not determine current equalizer.   mar 02, 2020 9:20:20 AM com.altera.debug.core WARNING: Could not determine current equalizer.   mar 02, 2020 9:20:25 AM com.altera.debug.core WARNING: Couldn't grab settings for channel LINK|1|slave_8000|pcie_gen.pcie_avmm_dma_inst|pcie_a10_hip_0|5   mar 02, 2020 9:20:30 AM com.altera.debug.core WARNING: Could not determine current equalizer.   mar 02, 2020 9:20:35 AM com.altera.debug.core WARNING: Could not determine current equalizer.   mar 02, 2020 9:20:40 AM com.altera.debug.core WARNING: Could not determine current equalizer.   mar 02, 2020 9:20:45 AM com.altera.debug.core WARNING: Could not determine current equalizer.   mar 02, 2020 9:20:50 AM com.altera.debug.core WARNING: Could not determine current equalizer.   mar 02, 2020 9:20:55 AM com.altera.debug.core WARNING: Couldn't grab settings for channel LINK|1|slave_8000|pcie_gen.pcie_avmm_dma_inst|pcie_a10_hip_0|4   mar 02, 2020 9:21:00 AM com.altera.debug.core WARNING: Could not determine current equalizer.   mar 02, 2020 9:21:05 AM com.altera.debug.core WARNING: Could not determine current equalizer.   mar 02, 2020 9:21:10 AM com.altera.debug.core WARNING: Could not determine current equalizer.   mar 02, 2020 9:21:15 AM com.altera.debug.core WARNING: Could not determine current equalizer.   mar 02, 2020 9:21:20 AM com.altera.debug.core WARNING: Could not determine current equalizer.   mar 02, 2020 9:21:25 AM com.altera.debug.core WARNING: Couldn't grab settings for channel LINK|1|slave_8000|pcie_gen.pcie_avmm_dma_inst|pcie_a10_hip_0|3   mar 02, 2020 9:21:30 AM com.altera.debug.core WARNING: Could not determine current equalizer.   mar 02, 2020 9:21:35 AM com.altera.debug.core WARNING: Could not determine current equalizer.   mar 02, 2020 9:21:40 AM com.altera.debug.core WARNING: Could not determine current equalizer.   mar 02, 2020 9:21:45 AM com.altera.debug.core WARNING: Could not determine current equalizer.   mar 02, 2020 9:21:50 AM com.altera.debug.core WARNING: Could not determine current equalizer.   mar 02, 2020 9:21:55 AM com.altera.debug.core WARNING: Couldn't grab settings for channel LINK|1|slave_8000|pcie_gen.pcie_avmm_dma_inst|pcie_a10_hip_0|2   mar 02, 2020 9:22:00 AM com.altera.debug.core WARNING: Could not determine current equalizer.   mar 02, 2020 9:22:05 AM com.altera.debug.core WARNING: Could not determine current equalizer.   mar 02, 2020 9:22:10 AM com.altera.debug.core WARNING: Could not determine current equalizer.   mar 02, 2020 9:22:15 AM com.altera.debug.core WARNING: Could not determine current equalizer.   mar 02, 2020 9:22:20 AM com.altera.debug.core WARNING: Could not determine current equalizer.   mar 02, 2020 9:22:25 AM com.altera.debug.core WARNING: Couldn't grab settings for channel LINK|1|slave_8000|pcie_gen.pcie_avmm_dma_inst|pcie_a10_hip_0|1   mar 02, 2020 9:22:30 AM com.altera.debug.core WARNING: Could not determine current equalizer.   mar 02, 2020 9:22:35 AM com.altera.debug.core WARNING: Could not determine current equalizer.   mar 02, 2020 9:22:40 AM com.altera.debug.core WARNING: Could not determine current equalizer.   mar 02, 2020 9:22:45 AM com.altera.debug.core WARNING: Could not determine current equalizer.   mar 02, 2020 9:22:50 AM com.altera.debug.core WARNING: Could not determine current equalizer.   mar 02, 2020 9:22:55 AM com.altera.debug.core WARNING: Couldn't grab settings for channel LINK|1|slave_8000|pcie_gen.pcie_avmm_dma_inst|pcie_a10_hip_0|0  

Connected reconfig clock and resets

 

        pcie_a10_hip_0_xcvr_reconfig_clk_clk    => clk_100mhz_1,

        pcie_a10_hip_0_xcvr_reconfig_reset_reset => '0',

        pcie_a10_hip_0_reconfig_pll0_clk_clk    => clk_100mhz_1,

        pcie_a10_hip_0_reconfig_pll0_reset_reset => '0',

        pcie_a10_hip_0_reconfig_pll1_clk_clk    => clk_100mhz_1,

        pcie_a10_hip_0_reconfig_pll1_reset_reset => '0',

 

 

SOF file used has also ttk enabled for native xcvr intarfaces which

are working fine on its own - but not visible when used together with pcie ttk hip.

 

0 Kudos
4 Replies
SSilu
Beginner
1,124 Views

I'v managed to run toolkit with minimal project. However it seems reconfiguration interface for rx is not active - it means I cant set prbs pattern or loopback. Also both tx and rx report wrong link speed 5G - I expect 8G for PCIe gen 3 hip. Is running ADME with PCIe HIP supported at all?pcierx.png

0 Kudos
SengKok_L_Intel
Moderator
1,124 Views

Hi,

 

This is not suggested to use TTK for PCIe IP interface for Arria 10 as this does not work well.

 

Regards -SK Lim

0 Kudos
SSilu
Beginner
1,124 Views

Thank you good to know. May I suggest you disabling this option in Qsys for Arria 10 family to prevent loosing time trying to set it up.

0 Kudos
SengKok_L_Intel
Moderator
1,124 Views

Thank you for the feedback, and I will take note of it.

0 Kudos
Reply