Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
20405 Discussions

PHYLite LVDS input


Hi All,

I'm trying to integrate AD9613 ADC (250 MHz LVDS DDR interface) to Cyclone 10 GX device and I would appreciate any help on fixing timing for that.

I've tried to implement the interface using GPIO first, passing clock through "source-synchronous" PLL first (+ a manually adjusted phase shift). For my best attempt (using 900 ps shift), TimeQuest shows slacks circa -0.6 ns both on Setup and Hold in the slow corner. Using different phase shift values, I can move slacks more to Setup or more to Hold, but total slack is more than 1 ns (which I believe is unacceptable).


Reading forums and docs (especially AN 756) I found that GPIO could be simply too slow for implementing 250 MHz input and that PHYLite core usage is recommended.

However, I can't figure out how to use PHYLite in my case. Please would anyone help.

In particular, I'm lost with:

1. How to setup LVDS inputs with PHYLite?

AN 756 (1.4.4) says "You can manually set the pin to use 3.0V/2.5V I/O standard through the Quartus Prime assignment editor".

I've done that (also put IO Standard = None in PHYLite). Fitter now gives "Error(16680): I/O pin DATA_p_6(n) has the LVDS I/O standard assigned to it, however the I/O lane cannot contain pins with the LVDS I/O standard. Modify your design so that pins in the I/O lane are not assigned the LVDS I/O standard."

2.  Do I have to physically pass the same signal (ADC clock) through 2 separate IO buffers (2 separate pins)?

If I simply connect DCO_p (ADC clock) both to strobe and ref_clock of PHYLite (as in AN 756 figure 4), fitter complains about incorrect IO buffer configuration. This can be fixed if I pretend to use separate clock and strobe signals.


Any help would be greatly appreciated.





The ADC is running at 250 MHz, LVDS DDR interface (4 ns period, 2 ns unit). Clock (DCO pins) is delayed after DATA for 0.4..1.0 ns (0.7 +/- 0.3 ns). Thus, the interface is not "center-aligned", but close to it.

Based on AN 433 I've put the following constraints (I would also appreciate if anyone would check if those constraints are correct):


set adcPeriod 4.000
# tSkew is 0.4 - 0.7 - 1.0 ns (min - typical - max). This equals to 0.7 ns shift +/- 0.3 skew.


# Virtual ADC clock (edge-aligned with data)
create_clock -name adcVirtualClk -period $adcPeriod
# DCO clock
create_clock -name adcDry -period $adcPeriod -waveform { 0.7 2.7 } [get_ports {DCO_p}]
# Skew method delays (see p. 49)
set_input_delay -clock adcVirtualClk -max 0.3 [get_ports DATA_*]
set_input_delay -clock adcVirtualClk -min -0.3 [get_ports DATA_*] -add_delay
set_input_delay -clock adcVirtualClk -clock_fall -max 0.3 [get_ports DATA_*] -add_delay
set_input_delay -clock adcVirtualClk -clock_fall -min -0.3 [get_ports DATA_*] -add_delay


# Set false path (see p. 51-52)
set_false_path -setup -fall_from [get_clocks adcVirtualClk] -rise_to [get_clocks adcDry]
set_false_path -setup -rise_from [get_clocks adcVirtualClk] -fall_to [get_clocks adcDry]
set_false_path -hold -fall_from [get_clocks adcVirtualClk] -fall_to [get_clocks adcDry]
set_false_path -hold -rise_from [get_clocks adcVirtualClk] -rise_to [get_clocks adcDry]



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6 Replies


Recommend you to use GPIO Intel FPGA IP ( for your application. Additionally refer to following link to understand supported I/O standards and corresponding banks.


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Hi Ash_R_Intel,

thank you for your answer, I will re-read these docs.


Should I be able to close 250 MHz timing using GPIO Intel FPGA IP?

So far the best I could get was [-0.72 Setup slack, -0.286 Hold slack] for "Slow 100C" corner (so I need about +1 ns into valid data window). Any clue on what is to be tried?


Please would you also confirm that:

1. It is not possible to use PHYLite core with LVDS inputs (need to convert them to something like HSTL on the board level).

2. I need both clock and strobe come from outside of the chip, if using PHYLite


Thanks in advance,



P.S. the chip is 10CX220YU484I6G

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Which path are you getting the negative slack? The constraints are specified only for the periphery clock and the data and they seems to be fine to me. You can also try the system level constraints as specified in AN 433,

How about the core logic constraints? Request you to analyze the path of negative slack in more detail.

PHYLite IP is mostly meant of DDR memory interface type applications. It does not support LVDS IO standard.


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Hi Ash_R,


there is almost no logic yet, just a LED driver to make the input used (not optimized out).


The code is below.

ADC clock (DCO_p/DCO_n) is first fed into IOPLL (source-synchrounous compensation mode, +700 ps phase shift, 250 MHz in, 250 MHz out) and then driven to GPIO IP instance (data bits are in DATA_X_p/DATA_X_n).


Attached are reports for the "Slow 100C" corner, same pin (DATA_10). "Slow -40C" is worse (-0.702 Setup, -0.435 Hold), Fast corners are better.



// ADC input

wire [23:0] adcRaw;
wire adcLocked;
wire adcClock;
wire adcRawValid;

adc_pll adcClockPll (
    .locked(adcLocked), // locked.export
    .outclk_0(adcClock), // outclk0.clk
    .refclk(DCO_p), // refclk.clk
    .rst(~startUpReset_n) // reset.reset

adc_gpio adcInput (
    .ck(adcClock), // ck.export
    .dout(adcRaw), // dout.export
       DATA_p_0, DATA_p_1, DATA_p_2, DATA_p_3,
       DATA_p_4, DATA_p_5, DATA_p_6, DATA_p_7,
       DATA_p_8, DATA_p_9, DATA_p_10, DATA_p_11
    }), // pad_in.export
       DATA_n_0, DATA_n_1, DATA_n_2, DATA_n_3,
       DATA_n_4, DATA_n_5, DATA_n_6, DATA_n_7,
       DATA_n_8, DATA_n_9, DATA_n_10, DATA_n_11
    }) // pad_in_b.export

assign adcRawValid = adcLocked;


assign FPGA_LED1 = (adcRaw > 24'hFF00FF);    // Make ADC data used (prevent optimizing-out)



Related pin-out:



## BANK 2A

set_location_assignment PIN_Y1 -to DATA_n_6
set_location_assignment PIN_Y2 -to DATA_p_6
set_location_assignment PIN_Y6 -to DATA_n_3
set_location_assignment PIN_Y7 -to DATA_p_3
set_location_assignment PIN_AA7 -to DATA_n_1
set_location_assignment PIN_AA8 -to DATA_p_1
set_location_assignment PIN_V8 -to DATA_n_7
set_location_assignment PIN_U8 -to DATA_p_7
set_location_assignment PIN_AB1 -to DATA_n_4
set_location_assignment PIN_AA1 -to DATA_p_4
set_location_assignment PIN_V2 -to DATA_n_11
set_location_assignment PIN_W2 -to DATA_p_11
set_location_assignment PIN_T1 -to DATA_n_10
set_location_assignment PIN_R1 -to DATA_p_10
# set_location_assignment PIN_V1 -to DCO_n
set_location_assignment PIN_U1 -to DCO_p
set_location_assignment PIN_V3 -to DATA_n_9
set_location_assignment PIN_U3 -to DATA_p_9
set_location_assignment PIN_AA4 -to DATA_n_5
set_location_assignment PIN_AB3 -to DATA_p_5
set_location_assignment PIN_W3 -to DATA_n_8
set_location_assignment PIN_W4 -to DATA_p_8
set_location_assignment PIN_AB4 -to DATA_n_2
set_location_assignment PIN_AB5 -to DATA_p_2
set_location_assignment PIN_AB9 -to DATA_n_0
set_location_assignment PIN_AB8 -to DATA_p_0

set_instance_assignment -name IO_STANDARD LVDS -to DATA_n_0 -entity Main
set_instance_assignment -name IO_STANDARD LVDS -to DATA_p_0 -entity Main
set_instance_assignment -name IO_STANDARD LVDS -to DATA_n_1 -entity Main
set_instance_assignment -name IO_STANDARD LVDS -to DATA_p_1 -entity Main
set_instance_assignment -name IO_STANDARD LVDS -to DATA_n_2 -entity Main
set_instance_assignment -name IO_STANDARD LVDS -to DATA_p_2 -entity Main
set_instance_assignment -name IO_STANDARD LVDS -to DATA_n_3 -entity Main
set_instance_assignment -name IO_STANDARD LVDS -to DATA_p_3 -entity Main
set_instance_assignment -name IO_STANDARD LVDS -to DATA_n_4 -entity Main
set_instance_assignment -name IO_STANDARD LVDS -to DATA_p_4 -entity Main
set_instance_assignment -name IO_STANDARD LVDS -to DATA_n_5 -entity Main
set_instance_assignment -name IO_STANDARD LVDS -to DATA_p_5 -entity Main
set_instance_assignment -name IO_STANDARD LVDS -to DATA_n_6 -entity Main
set_instance_assignment -name IO_STANDARD LVDS -to DATA_p_6 -entity Main
set_instance_assignment -name IO_STANDARD LVDS -to DATA_n_7 -entity Main
set_instance_assignment -name IO_STANDARD LVDS -to DATA_p_7 -entity Main
set_instance_assignment -name IO_STANDARD LVDS -to DATA_n_8 -entity Main
set_instance_assignment -name IO_STANDARD LVDS -to DATA_p_8 -entity Main
set_instance_assignment -name IO_STANDARD LVDS -to DATA_n_9 -entity Main
set_instance_assignment -name IO_STANDARD LVDS -to DATA_p_9 -entity Main
set_instance_assignment -name IO_STANDARD LVDS -to DATA_n_10 -entity Main
set_instance_assignment -name IO_STANDARD LVDS -to DATA_p_10 -entity Main
set_instance_assignment -name IO_STANDARD LVDS -to DATA_n_11 -entity Main
set_instance_assignment -name IO_STANDARD LVDS -to DATA_p_11 -entity Main
# set_instance_assignment -name IO_STANDARD LVDS -to DCO_n -entity Main
set_instance_assignment -name IO_STANDARD LVDS -to DCO_p -entity Main



Project settings:


set_global_assignment -name DEVICE 10CX220YU484I6G
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256

set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL ON
set_global_assignment -name TIMING_ANALYZER_DO_REPORT_TIMING ON
set_global_assignment -name IO_PLACEMENT_OPTIMIZATION ON
set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS ON
set_global_assignment -name ROUTER_REGISTER_DUPLICATION ON
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF

set_global_assignment -name FAST_PRESERVE OFF -entity main
set_global_assignment -name OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT ON
set_global_assignment -name FLOW_ENABLE_EARLY_PLACE ON
set_global_assignment -name VERILOG_FILE main.v
set_global_assignment -name SDC_FILE main.sdc


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Should I be able to close 250 MHz timing using GPIO Intel FPGA IP on Cyclone 10 GX?

Does anyone have a similar experience? Did anyone intergrated high-speed ADCs with Cyclone 10 GX?


If it is totally impossible to achieve 250 MHz using LVDS+GPIO, we will need to redesign the board, converting inputs from LVDS+GPIO to HSSTL+PHYLite.

This would be unfortunate, of course, but it would be double-unfortunate if we do it wrong %-) So I would also like to clarify all the details before doing so, because PHYLite docs are also a bit vague to me (or, may be, I'm simply too stupid - anyway, I still have questions).

In particular, AN 756 Use case 1 and Figure 4 seems to be exactly my case. Considering there is an ADC-generated clock and data lines:

1. Are STROBE_IN and REF_CLOCK exactly the same signal (ADC clock)?

2. Should STROBE_IN and REF_CLOCK be routed to different IO pads externally (do I need a clock fanout buffer)?

3. Are there any special requirements for those pins? REF_CLOCK should probably be a global clock pin, what about STROBE_IN?

Had anyone used PHYLite for reading ADC?


Thanks in advance,

any help is really valuable.


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