PLL Tolerance [ppm] in Cyclone V

[CS_PI]

Hi all, I use the Cyclone V on the Terasic DE1-SoC and like to know the PLL tolerance in ppm by increasing the 50 MHz input to 160 MHz.

Thanks a lot for your support!

[Farabi]

Hi, 

This depends on the clk osc used on the board. Can check the datasheet of the oscillator.  Normally, REFCLK input clock is feed by <50ppm clock osc. 

regards,
Farabi

[CS_PI]

That's true, but the tolerance of the oscillator should be added to the unknown and requested PLL tolerance of the Cyclone V to get something like a total clock tolerance.

[ak6dn · Accepted solution]

You are confusing two separate concepts.

There is clock source 'accuracy', which is what the PPM specification represents. For example, you might have a 50MHz oscillator with a +/-100 PPM initial accuracy. So this gives the nominal accuracy that you would measure on a frequency counter, for example.

The PLL will perform an integer multiply / divide on this value to give the output frequency. So do the multiply/divide calculation on the minimum input frequency (50MHz - 100ppm) and on the maximum input frequency (50MHz + 100ppm) to find the PLL output limits.

Now all clock sources have short term jitter characteristics, and PLL circuits have short term jitter characteristics as well. This value of the device will affect the cycle-cycle timing characteristics (ie, between successive rising edges of the clock). Typically given in picoseconds.

Here is an example of using a 50MHz 100ppm source multiplied by 6 to give 300MHz output, and a 150MHz 100ppm source multiplied by 2 to give the same 300MHz output.

As the table shows, the results are EXACTLY the same at the output of the PLL. So using a higher input frequency at the same PPM tolerance does not make a difference on the generated output.

MHz	ppm	tolerance	minimum	maximum	multiplier	minimum	maximum
50,000,000	100	5,000	49,995,000	50,005,000	6	299,970,000	300,030,000
150,000,000	100	15,000	149,985,000	150,015,000	2	299,970,000	300,030,000

The input jitter of the clock sources effect on the PLL depends on the PLL loop characteristics of the particular FPGA device. That is not as easy to quantify in simple table. The PLL has a filtering effect on the input source jitter, and there is an inherent PLL jitter on the generated output. But since the output frequency is the same the for each PLL case the jitter should be very similar for each.

So long story short just changing the input frequency from 50MHz to something like 150MHz, assuming you want the same output frequency, is a wash. No benefit.

[Farabi]

Hello, 

We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

best regards,

Farabi

[angelhart]

This relies upon at the clk osc used at the board. Can take a look at the datasheet of the oscillator. Normally, REFCLK enter clock is feed by <50ppm clock osc. That`s true, however the tolerance of the oscillator must be brought to the unknown and asked PLL tolerance of the Cyclone V to get some thing like a complete clock tolerance. We do now no longer acquire any reaction from you to the preceding question/reply/solution that I even have provided. This thread might be transitioned to network assist. If you've got got a brand new question, experience loose to open a brand new thread to get the assist from Intel experts. Otherwise, the network customers will retain that will help you in this thread. Thank you.