PLL creation with IP Catalog (refclock less than 5MHz)

[GuilhermeBarbosa]

Hello,

I'm a college graduate from Brazil at Federal Technological University of Paraná and I'm having problems setting up a PLL from IP catalog, would you please help me?

I've been assigned to demodulation in a visible light communication project and my goal is to set a PLL for clock recovery of a PPM signal.

Since we are working with a DE10 NANO (Cyclone V SE BASE - 5CSEBA6U23I7), our first solution would be using the IP catalog.

However, the components available under "LIBRARY>>BASIC FUNCTIONS>>CLOCKS, PLL AND RESETS>>PLL" doesn't seem to work for us since our signal is 3.75 MHz and IP catalog PLL's minimum frequency seems to be 5 Mhz.

Am I missing something on the megawizard window? 

Are there other available IP catalog components I could try creating in order to set up a PLL which refclock0 is a 3.75 Mhz PPM signal?

Thanks in advance,
Guilherme Barbosa

[sstrell]

Where are you seeing such a slow clock?  The board provides a number of clocks.  If you are saying you need to generate 3.75 MHz, that should be set as an output clock, not as the reference clock.

[GuilhermeBarbosa]

The FPGA I'm working with will act as a receiver for a wireless 3.75MHz signal. The signal will be transmitted by another FPGA. (attached is a screenshoot of the waveform of the 3.75MHz signal).

Therefore, I need to recover the 3.75MHz clock from the signal wave itself and assure it will be phased by 90 degrees so we can perform the signal deserialization later on.

Even though we'll use the 50MHz standard clock for the board operation, our plans were having both refclock and output clock set as 3.75MHz. Refclock as the signal wave received and output clock as the original clock signal phased by 90 degrees.

As far as I know, that configuration is feasable due to our PPM signal having only two positions (0 or 1), but IP megawizard is preventing me from creating a PLL with a refclock lower than 5MHz and confirm if the component would work as intended.

Is there a way to generate a PLL through IP catalog with refclock lower than 5MHz?

[ShengN_Intel]

Hi,

No. The min legal refclk frequency is 5mhz.

Thanks,

Regards,

Sheng

[FvM]

Hi,
besides frequency range problem, PLL can only synchronize to a continuous clock signal. Red encircled signal rather requires some kind of CDR circuit that reconstructs a continuous clock matching signal edges. Cyclone V has no hardware CDR features, soft CDR can be however implemented utilizing PLL dynamic phase shift.

Regards
Frank

P.S.: Not sure if you need to exactly synchronize to signal clock. If you just want to decode the (apparently Manchester encoded) data stream, an UART approach with sufficient oversampling ratio is probably the straightforward way.