PLL reconfiguration problem

[Altera_Forum]

Hi, 

i want to reconfigure a pll by sending my data chain.When i create my pll with 40 MHz with megawizard it works perfectly.I can set various frequencies.  But when i create my pll with 65 MHz with megawizard it does not work. i tried others frequencies(50 MHz,60 MHz),but they do not work. I use quartus II 8.0. Thanks Sacko

[Altera_Forum]

Hi Sacko, 

 in order to better understand your problem I would like to ask you, which FPGA chip and which Development board are you using? The ALTPLL can normally manage the internal PLLs and generate the frequency you want according to the FPGA you have available. I would like to ask you also which reference frequency are you using to feed the ALTPLL block and which error does it present to you in case you get one by the compilation process.  BR,  Giovanni

[Altera_Forum]

Hi, 

it is a board with an cyclone III EP3C40. My input frequency is 50 MHz. there is no error in compilation report.all things is fine.  Only when i send my configuration data to pll(over pio) it does not output a frequency. I will try to compile the PLL with 40 MHz and see if it stay stable. Thanks

[Altera_Forum]

i found that the pll is losing lock when i set the output to be 65 Mhz. 

But when the output stting is 40 MHz it works fine. any idea? Thx.

[Altera_Forum]

Is your pll controlling any signal that goes out of the FPGA, on the same bank than your 50MHz input? If yes, too many simultaneous switching signals on a bank output could introduce noise that makes the pll loose its lock, especially if the bank's IO supply isn't decoupled enough.

[Altera_Forum]

i found why it did not work before.I was sampling my data into the pll at the clock falling edge. 

I think at 40 MHz the data was enough stable that the timing was little bit ok. May be it can help anyone further. Thx all of you for replying me Sacko.