PS and JTAG

[HT4]

I am using Cycole IV GX and plan to use MAX10 and flash for PS configuration.

1. Can I combine both configuration methods: PS and JTAG together on my board? I don't see in configuration methods in cyclone IV. if not then how can I use system tap logic analyzer for real time debugging in PS configuration mode?
2. between figure 8-13 in document for Cyclone IV configuration (handbook) and figure 3 in UG-01082 there is inconsistency for pin connections. which one should I use? I assume the second one is more accurate. is that correct?

Thanks

[ShafiqY_Intel]

Hi HT, 1. If you refer to Configuration Scheme (Table 8-3, Table 8-4 and Table 8-5 on page 172 Cyclone IV Handbook), you can combine AS, PS and JTAG together on your board. However, when you want to select which configuration scheme you want to use, you need to select the correct MSEL setting on your board. If you look at Intel Cyclone IV Dev kit schematic diagram, you can see how we design MSEL setting on our board. - Download this link & run as Administrator http://fpgadownload.intel.com/outgoing/devkit/12.1/cycloneIVGX_4cgx150_fpga_v12.1.0.exe - Goes to <Installation directory>\kits\cycloneIVGX_4cgx150_fpga\board_design_files\cycloneIVGX_4cgx150_fpga\schematic - Open schematic diagram c4gx_f896_host_b.pdf for more details. 2. Figure 8-13 in Handbook is more accurate. CONF_DONE and nSTATUS for Cyclone IV should be Directional (open-drain) pin. For more information and details regarding pin connection, please refer to Cyclone IV Device Family Pin Connection Guidelines (Configuration/JTAG Pins section) Link for Configuration Scheme Handbook = https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-iv/cyclone4-handbook.pdf#page=172 Link for Cyclone IV Device Family Pin Connection Guidelines (Configuration/JTAG Pins section) = https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/dp/cyclone-iv/pcg-01008.pdf#page=2 I hope this will help. Thanks.

[HT4]

Hi Thanks for your explanations. I was not clear about first question: I want to use just one connector for programmer. in the schematic you sent, there are two connectors so it is easy just by choosing MSEL pins, configure FPGA in JTAG mode but what about having only one connector. as you see in datasheet, for AS and JTAG it is possible because in both configuration I will use FPGA as bridgely to program but here I am using mainly CPLD as bridge so how I can configure them through one connector?

Thanks

[HT4]

did you see my question again to your response?

[ShafiqY_Intel]

Hi,

I'm really apologize for late reply. I got an urgent project in last month.

May I know your status in this issue? Are you able to solve and find the solution?

😉