Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
21588 Discussions

Parallel 50 Ohm with Calibration

Altera_Forum
Honored Contributor II
‎08-04-2011 03:19 AM
1,704 Views

My customer put input pins with the following assignment on Stratix IV. 

 

IO: Input 

IO standard: SSTL-18 Class I 

Termination: Parallel 50 Ohm with Calibration 

(RUP and RDN are connected to resistors respectively) 

 

The customer configured their FPGA and measured the input resistance at the pins. 

But the customer said that parallel termination seems not working. 

I reproduced this issue on SIV dev kit. 100ohm resistance was not monitored at all on these input pins. 

 

Have you ever measure the resistance of Parallel 50 Ohm with Calibration on your board? 

I have no idea why 100ohm resistance was not monitored
0 Kudos

Link Copied

1 Reply
Altera_Forum
Honored Contributor II
‎08-11-2011 06:51 AM
825 Views

And how exactly did you measure?

0 Kudos
Copy link
Reply

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.