Programmable Devices

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Programmable Devices

Discussions

Simulation Tools

DevKit General Purpose I/O question

MAX10 can't accept 125 MHz clock without timing violations

Flash Programmer, EPCS Reserved Fields are non-zero

Manually applied Clock Data Recovery in Arria II GX

Device problem(EP4CGX150DF27I7)

altera cyclone V banks

Asserting DEV_CLRn during configuration

Dynamic io delay

What is the Slew Rate VALUE of Cyclone IV?

MAX10 ADC & GPIO restrictions

Using Altera GPIO Lite Ip core as bidirectional DDR

Bus error when trying to write to memory

FPGA to HPS interrupts

Differential input pair LVDS for the ADC5272 in Cyclon 3

Featured Content

EPM3064ATC44-7N and EPM3064ATI44-10N

p0_pin_perst_n remains asserted when implementing GTS AXI Streaming intel FPGA IP for PCI Express

Deserializers in Agilex 3 series

Re: Download speed

Re: Quartus Prime Design Software - JTAG usage