Are current design uses a Cyclone IV E device, EP4CE75U19I7N, and the Micron Synchronous FLASH device, PC28F128P33BF60A. As you are aware the Flash device has been obsolete.
Thanks in advance
Yes, you can use MAX 10 with the PFL IP to perform FPP configuration to any FPGA device. Please refer to the PFL user guide on the PFL IP supporting flash devices:
Cyclone IV FPP mode only support 8 bits data width. You should refer to the FPP Configuration chapter from the Cyclone IV device handbook to further understand this:
The PFL IP (in MAX 10 ) act as the bridge between the flash device and Cyclone IV device to perform:
a) program flash memory devices with the MAX10 device JTAG interface.
b) configuration (e.g. FPP or PS mode) to the Cyclone IV device
You should read the PFL IP user guide to understand usage and settings that you need to perform the FPP mode. Also you can refer to this Configuration walk through from link below which has some useful examples:
You can refer to the Cyclone IV GX development kit schematic as reference in the link below. Even though the Cyclone IV GX development kit is built using PS mode (1 bit data), the difference is the 8 bits data and MSEL pins connection for FPP mode.
My name is Dov, and I work together with Yehuda. I have a question as well.
In addition to FPGA configuration at power up, we need to support remote update of the FPGA configuration. There has to be a way that we can program the flash device from the Cyclone iV via the MAX10 (we don't have access to the MAX10 JTAG during remote update).
Is this possible? Thanks, Dov
Yes, you are correct about PFL can only be use with Quartus programmer via JTAG interface. I checked with my colleague who specialize in Embedded area, it seems that user can consider to use NIOS II with Avalon Tri-State Conduit components in FPGA to access the CFI flash. You can refer to chapter 5.2.6. Nios II Processor Booting from CFI Flash in the Embedded Design handbook for the details:
Also, you can refer to the Cyclone V dev kit reference manual, schematic and BUP(board portal update) design as reference:
Most of the FPGA dev kit come with the BUP(board portal update) design that utilize NIOS II with Avalon Tri-State Conduit components in FPGA. While the PFL in CPLD is use to perform the FPPx16 configuration to Cyclone V.
You can refer to chapter "FPGA Programming from Flash Memory" for some explanation and Figure 2–4. PFL Configuration on the FPGA-CPLD-flash connection from the Cyclone V GT dev kti reference manual: