Phased Clock

[VYoung]

Are there any Intel SoC FPGAs that provide a clock manager with different phased clock outputs? e.g. One 100 MHz input with four 200 MHz phased outputs (0 degree, 90 degrees, 180 degrees, and 270 degrees).

If yes, what is the FPGA family (i.e., Agilex, Stratix, Arria, MAX, Cyclone)?  And what is the device part number within the family?

[FvM]

Hi,
the feature is available in any recent Intel FPGA, e.g. the mentioned families.

[JingyangTeh_Altera]

Hi VYoung

All the intel families support the feature you are looking for.

You could look for the PLL Soft Core IP which are supported for all the Intel FPGA devices.

There are 2 types of PLL cores that are available and are supported in different FPGA families.

You could look into the "supported devices" in the documents below:

https://www.intel.com/content/www/us/en/docs/programmable/683285/18-1/core-user-guide.html

https://www.intel.com/content/www/us/en/docs/programmable/683359/17-0/altera-phase-locked-loop-ip-core-user-guide.html

In the Soft IP you could select the number of clock signals, different frequency for each signals and also adjust the phase difference.

Regards

Jingyang, Teh

[JingyangTeh_Altera]

Hi VYoung

Any update on this case?

Do you have any more question regarding the PLL IP?

Regards

Jingyang, Teh

[VYoung]

Hi Teh,

I found the following PLL Block Diagram for the Intel FPGAs:

It kind of implies that there are only 2 clock outputs for the PLL.  My design uses 4 phase shifted 200 MHz clock outputs (0, 90, 180, 270 degrees phase shift).  The input clock is 100 MHz.  Can the PLL hard core provide this?   You mention the PLL Soft Core IP can provide this, but will the PLL Soft Core IP use a lot of fabric resources?

Thanks,

VYoung

[JingyangTeh_Altera]

Hi Vyoung

Yes. In the the IP configuration the you could select the numbers of clocks output you would like and the phase difference in between the clocks.

Please refer to the diagram below:

As for the fabric resource I do not have that information but I assume that it would not take up a lot of resource as it is a common IP that is being used.

Regards

Jingyang, Teh

[JingyangTeh_Altera]

Hi Vyoung

Any update on this case?

Are you still facing any problem with the Phased Clock IP?

Regards

Jingyang, Teh

[JingyangTeh_Altera]

Hi

Since a solution have been provided and no feedback was received, I shall set this thread to close pending. If you still need further assistance, you are welcome reopen this thread within 20days or open a new thread, some one will be right with you. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

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Regards

Jingyang, Teh