Please explain the following

Altera_Forum · ‎09-29-2011

I have one line in my VHDL test bench file as follows CONV_STD_LOGIC_VECTOR(16#100#+I*2,16) in for Loop integer I.

Could anyone please explain how can I plot this in waveform,

I know some basic like CONV_STD_LOGIC_VECTOR(16#200#,16) will convert that into HEX so I can drive 200 in waveform

Altera_Forum · ‎09-29-2011

I dont really understand your question. COuld you post more code in context?

Altera_Forum · ‎09-29-2011

I am having test bench vhdl using that I am doing simulation on quartus simulator tool to check the design and use the same kind of vector to test in real time. For that I need to give input address which is std logic vector.

At some point in test bench vhdl code I got like this

for I in 0 to 15 loop

BUS_ADDR_I <= CONV_STD_LOGIC_VECTOR(16#100#+I*2, 16);

....

.....

end loop;

I need to simulate this input address in waveform file How to decode this in to address bus?

Ex:

If it is like the following BUS_ADDR_I <= CONV_STD_LOGIC_VECTOR( 16#0210#, 16);

I'll drive address bus as 0x210

Altera_Forum · ‎09-30-2011

BUS_ADDR_I already is an address bus.

I still dont understand what you are trying to do.

Are you trying to wait between loop iterations?


for I in 0 to 15 loop
  BUS_ADDR_I <= CONV_STD_LOGIC_VECTOR(16#100#+I*2, 16);
  wait until rising_edge(clk) ;
end loop;