First of all, let me preface my post by stating I know I am attempting to do something that the language probably did not intend...now on with the question... :)
To illustrate the general question, I will consider the simple design example of a pipeline block. Envision a simple unit that provides a pipeline for a complex data type defined as a structure. Inside the unit, I can specify structure types as the left hand side of an assignment. This works because structures can be declared as signals.
Now, consider that I want to design the pipeline where the block utilizes the interface construct instead of structures. This works well externally, but it does not appear to work as well internally. The problem I run into is that interfaces, being more like modules, cannot be declared as signals. As a result, they cannot appear on the LHS of an assignment statement. Is there another game that can be played that has the affect of performing an assignment to an interface without actually using an assignment statement?
What if I want my output interface to be equal to my input interface? Can I define an interface task that performs this and circumvents the assignment issue. This would require that an interface type be the argument to a task - probably not possible.
Can this design task be accomplished using interfaces? I know many other ways to do it without using interfaces, but I am trying to find ways to fully utilize the interface construct.
Thanks.
