Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.
21615 Discussions

Power and ground pin decoupling capacitors

Altera_Forum
Honored Contributor II
3,071 Views

Hello everybody, 

 

In the Max II CPLD manual required Power and ground pin decoupling capacitors requirements are stated as follows: 

 

Board Decoupling Guidelines: 

 

 

Decoupling requirements are based on the amount of logic used in the device and the output switching requirements. As the number of I/O pins and the capacitive load on the pins increase, more decoupling capacitance is required. As many as possible 0.1-mf power-supply decoupling capacitors should be connected to the VCC and GND pins or the VCC and GND planes. 

 

 

This seems very big, around here we generally use 100 nF on uC pins.  

 

 

 

Opinions ? 

 

 

Thanks, 

Eric 

0 Kudos
8 Replies
Altera_Forum
Honored Contributor II
1,169 Views

I don't have the document here. Probably this is a typo. 

Usually you may need a single big capacitor in the 100uF range to decouple power supply in the middle-low frequency range, near the supply source. The capacitors located near device supply pins are 100nF or 10nF and these are for high decoupling frequencies. 

Generally speaking, if no further information is given in a component datasheet I use this rule of thumb: a 100nF and a 10nF for each supply pin.
0 Kudos
Altera_Forum
Honored Contributor II
1,169 Views

Super, thanks a bunch Cris72, I really appreciate your answer. 

 

Cheers, 

Eric
0 Kudos
Altera_Forum
Honored Contributor II
1,169 Views

Hello,  

I dont know if this the right place to this quetion, but some one know how obtain the capacitance of instances in a netlist file from Quartus II tool. 

 

I need to use the netlist file from Quartus tool, in the Nanosim tool from Synopsys, because there isn't any Altera tool to obtain the capacitance of a instance (resistor, transistor, capacitor, etc) of a FPGA design. 

 

Thank you for help.
0 Kudos
Altera_Forum
Honored Contributor II
1,169 Views

typically IBIS or HSPICE models are used, but i don't know if Nanosim supports them

0 Kudos
Altera_Forum
Honored Contributor II
1,169 Views

So, did you say that I can use the IBIS or HSPICE to obtain the capacitance from a Quartus netlist, did you? Because the Quartus netlist is a .vo file so I think they don't support.  

 

Do you know if I can set the Quartus to give me another kind of netlist file, like *.sp or *.spi file? These kind of files are supported by Nanosim tool. 

 

Thanks so much.
0 Kudos
Altera_Forum
Honored Contributor II
1,169 Views

maybe you should start a new thread and explain exactly what you are trying to do, because i don't quite understand

0 Kudos
Altera_Forum
Honored Contributor II
1,169 Views

Could you explain how I create a new thread here? 

Thank you for your help.
0 Kudos
Altera_Forum
Honored Contributor II
1,169 Views

scroll to the bottom of the list of topics and you will find a yellow button that says new topic 

 

thank you
0 Kudos
Reply