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Hi,
I m using altera-modelsim for my project. Quartus has generated a functional simulation model file(.vo). I see most of the altera libraries prebuild and mapped to my project. But when I simulate using my testbench, it fails reporting Error: (vsim-3033) /$$$$$$$$$$$$$/simulation/modelsim/$$$$$$$$$$_timestamp_051817_141152.vo(1564905): Instantiation of 'stratixv_io_ibuf' failed. The design unit was not found. My understanding is that this library is precompiled as a part of the altera-modelsim, and is present in the library list in my project. What could be the reason why the simulation stopped. Any directions?. Regards Jeebu Jacob ThomasLink Copied
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Just an additional information: I m using Modelsim from Quartus15 for simulation and the Quartus14 for generating the simulation file.
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Solved the problem. The design was in verilog, and the library support was available only for VHDL. Once I changed the netlist generation option from verilog to VHDL, the error issue got solved.
Why is there no library support in Verilog for StratixV ?. Or is it available?.- Mark as New
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There is, but perhaps you have a mixed-language design. Are you using the starter edition of Modelsim-Altera? I think it only supports a design that is all of one language or the other.
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Hi sstrell,
Thanks for the quick reply. Yes I m using the starter edition of Modelsim-Altera. And my design is mixed with verilog and system verilog. But Altera Tool information page confirms Mixed Support for Starter Edition too. https://www.altera.com/products/design-software/model---simulation/modelsim-altera-software.html Thanks and Regards Jeebu Jacob Thomas
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