Re: Problem simulating FIFO at Modelsim

Altera_Forum · ‎01-12-2011

Hello i used the FIFO from megawizard and i can't simulate it at modelsim, i am trying to add the altera_mf library but all my tries are worthless..

please help! This is my error

vsim work.tb_fifo#  vsim work.tb_fifo #  Loading work.tb_fifo#  Loading work.fifowrapper#  ** Warning: (vsim-3009)  - Module 'fifowrapper' does not have a `timescale directive in effect, but previous modules do.#          Region: /tb_fifo/u0#  Loading work.base#  ** Error: (vsim-3033) C:/DHW/Projetos/dmafifo/base.v(82): Instantiation of 'dcfifo' failed. The design unit was not found.#          Region: /tb_fifo/u0/fifo_inst#          Searched libraries:#              C:\DHW\Projetos\dmafifo\tb\work#  Error loading design

Altera_Forum · ‎01-12-2011

did you compile altera_mf into altera_mf or into work?

these docs should help:

http://www.altera.com/literature/hb/qts/qts_qii53001.pdf

http://www.altera.com/literature/hb/qts/qts_qii53025.pdf

you must not be using ModelSim-A(S)E?

Altera_Forum · ‎01-12-2011

yes i am using modelsim ASE.. it is possible?

I didnt compile them into work, can you tell me how? Going to read the docs you told me to. Thanks

Altera_Forum · ‎01-12-2011

ModelSim-ASE should have the altera_mf libraries precompiled and installed. however, from your simulation:

#         Searched libraries:
#              C:\DHW\Projetos\dmafifo\tb\work

it doesn't look like it is searching through all of the Altera libraries. in ModelSim's Libraries window, do you see just the work library or a list of various libraries?

Altera_Forum · ‎01-12-2011

i see all the libraries there but i can't make modelsim search theree

Altera_Forum · ‎01-14-2011

Hello ? = )

Altera_Forum · ‎01-14-2011

if you post some HDL i'll try and take a look. you can just isolate it to the test bench and FIFO

Altera_Forum · ‎01-14-2011

What kind of HDL you mean?


module fifowrapper(
                    // inputs:
                     rdclk,
                            rstn,
                            rdreq,
                    // outputs:
                     valid,
                     q
                  );
                        
input  rdclk;
input rdreq;
input rstn;
reg rdreqtemp;
reg wrclk;
reg wrreq;
output  q;
output reg valid;
wire  data;
reg  data_in;
assign data = data_in;
wire  usedw;
reg  contador;
reg  delay;
always@(posedge rdclk or negedge rstn)
  if (~rstn)
   begin
   valid <= 0;
   contador <= 0;
   data_in <= 0;
   wrreq <= 0;
    delay <= 0;
   end
  else
begin
        contador <= contador +1;
        valid <= 0;
        wrreq <= 0;
           if(usedw == 6'b100000)
            begin
                valid <= 1;
            end
            if(contador == 100000000)
            begin
                wrreq <=1;
                data_in <= data_in + 32'b00000000000000000000000000000001;
                contador <= 0;
            end
end
base    fifo_inst (
    .data ( data ),
    .rdclk ( rdclk ),
    .rdreq ( rdreq ),
    .wrclk ( rdclk ),
    .wrreq ( wrreq ),
    .q ( q ),
//    .rdempty ( rdempty_sig ),
//    .rdusedw ( usedw )
    .wrusedw ( usedw )
//    .wrfull ( wrfull_sig )
    );
endmodule

This is my wrapper

and this if my testbench


 `timescale 1 ns/1 ns
module tb_fifo;
parameter P_CLKPERIOD = 50;
reg tb_i_clk;
reg tb_i_rstn;
wire tb_valor;
//CLOCK DO SISTEMA EM 50ns - 20Mhz
initial tb_i_clk = 1'b1;
always# (P_CLKPERIOD/2) tb_i_clk <= ~tb_i_clk;
// RESET DO SISTEMA
initial
begin 
    @(posedge tb_i_clk);
    tb_i_rstn <= 0;
   # 10;
    @(posedge tb_i_clk);
    tb_i_rstn <= 1;
end
// BLOCO PRINCIPAL
fifowrapper u0(
    .rdclk (tb_i_clk),
    .rstn (tb_i_rstn),
    // outputs:
    .valid(tb_valor)
    //.q
    );
endmodule

Altera_Forum · ‎01-14-2011

can you post base.v too?

Altera_Forum · ‎01-14-2011

my base.v is the fifo itself made from megawizard