Problem with Gigabit Ethernet Clocks

[Altera_Forum]

Hi, 

 I am working in a design that includes a propietary MAC layer to the PHY Marvell Ethernet chip, using RGMII interface. The FPGA that I used to the design is a ARRIA GX II 260. I have defined all the constrains such as the AN477 document of Altera describes. When I compile a design that only has a test block and this MAC Layer, all works fine. The problem is with a more dense design, in which I include the same constraints and the same MAC Layer and the transmission doesn't work.  I tried to explore the timing report of Timequest, but it haven't information about the clocks that I have defined in my SDC file, and for this reason, it doesn't report anything.  Is it possible to delete all the temporal information of the project to make a compilation without previous information? Could it be a problem with timing?   Thanks a lot.

[Altera_Forum]

Define clocks in SDC first. This is very VERY important for the whole design and especially RGMII/GMII bus.

[Altera_Forum]

First of all, thank you for your answer.  

 I have defined the clocks propertly, and the Timequest shows me that the definitons are OK (in the Report SDC I could see the clocks involved in the RGMII tranmission), but ther isn't any report of this clocks and the path between the output of Dobule Data Rate Registers and the pins of the PHY Layer.  Thanks

[Altera_Forum]

Once the clocks are defined, you must ensure that all the I/O pins are constrained. There is one report called unconstrained paths that will tell you if some of the pins aren't constrained. 

When applying the SDC rules, check that the pin names match the one of your design. If the RGMII pins are constrained, Timequest should then tell you if the timing requirements are met. If they aren't, you'll find the failing paths in the report "top failing paths"

[Altera_Forum]

Clocks are not included in the path between DDRIO and FPGA pins, because clock is also generated using DDR primitives afaik (I am not sure actually).

[Altera_Forum]

Daixiwen, I have revised the report that you said but I didn't find any information about the RGMII transmission pins. The RGMII reception pins (RXD and RX_CTL) are present in the I/O report, but the transmission (TXD and TX_CTL) pins did not appear in this report. 

 Socrates, could you explain a little more your last comment? I don't understand it because my problem is constraining the pins, not the clocks.  I have revised the SDC definition and I didn't find any problem. Thank you so much for your help.

[Altera_Forum]

You can also check the warnings when you run Timequest, if some of your lines in the SDC script couldn't be executed for some reason, it will add a warning. Both the inputs and the outputs should be constrained.

[Altera_Forum]

Finally, we could find the problem. The definiton of the clock domains are wrong, and for this, Quartus did not apply the restriccions such as we want. Thanks for your help.

[Altera_Forum]

Yep, always check if clocks are defined correctly, then the possibility to run the design even with timing warnings rises alot :-)