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Problem with RAM: 2-PORT


Dear all,

I've been struggling with this issue lately and I could not find a solution, so I hope you can help.


I'm using a Cyclone V SoC, with which I would like to store in the internal ram of the FPGA the digitized signal coming from an ADC, and then export the data to a .txt file using the embedded microprocessor.

To do this, I have instanced the RAM 2-PORT IP, using it with two read/write ports and with two separate clocks for A and B ports. This is how the instantiation of the RAM looks in my VHDL:


port map(

address_a => ADDR_COUNTER, //10-bit counter increasing by 1 each clock cycle

clock_a => CLOCK_20, //20 MHz clock signal

enable_a => REG_1_HPS(11),

data_a => ADC_READ, //16-bit input signal from ADC

wren_a => REG_1_HPS(12),

q_a => RAM2DAC_OUT, //16-bit output signal to a DAC

address_b => REG_1_HPS(9 downto 0),

clock_b => REG_1_HPS(10),

enable_b => not REG_1_HPS(11),

data_b =>REG_1_HPS(31 downto 16),

wren_b => REG_1_HPS(13),

q_b => REG_0_HPS(15 downto 0),



The two 32-bit registers REG_1_HPS (output) and REG_0_HPS (input) are connected in Platform Designer as Avalon MM Slaves to the H2F_AXI_MASTER to interface with the processor.


Running a C program sets high the bits 11 and 12 of REG_1_HPS, and the signal sent to the ADC is correctly seen at the oscilloscope connected to the DAC.


What I fail to do is to "export" the data stored on the RAM to a .txt file. The part of the C program which should do this is the following (the various variables are declared earlier in the code):


fp = fopen(filename,mode);

*(uint32_t *)reg_1 = 0x00000000;

for (i=0; i<1024; i++) {

*(uint32_t *)reg_1 |= i;


*(uint32_t *)reg_1 |= 1<<10;


fprintf(fp,"%d\r\n",*(uint32_t *)reg_0);


*(uint32_t *)reg_1 |= 0<<10;




Doing so however gives all 0s in reg_0, instead of the data which should compose the signal I see at the DAC, and which it is stored in the RAM. Can someone give me a hint on what I'm doing wrong?

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2 Replies
Honored Contributor III

You've got a number of ports duplicated in the port map, which I presume are supposed to be _b ports instead of _a. I'm surprised this was synthesizable without warnings.



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Sorry, that was a mistyping, now I have corrected it (of course, like that as you say synthesis would have probably failed).