Problem with WHILE Loop

[Altera_Forum]

I am currently trying to compile and simulate a vhdl ROM file. I am having problem with the while loop, which is used to read the ROM. The following is the vhdl-code: 

 entity mc8051_rom is  generic (c_init_file : string := "mc8051_rom.dua");  port (clk : in std_logic; -- clock signal reset : in std_logic; -- reset signal rom_data_o : out std_logic_vector(7 downto 0); -- data output rom_adr_i : in std_logic_vector(15 downto 0)); -- adresses;   end mc8051_rom;  architecture sim of mc8051_rom is  type rom_type is array (65535 downto 0) of bit_vector(7 downto 0); --originally (65535 downto 0) and(7 downto 0) signal s_init : boolean := false;  begin  ------------------------------------------------------------------------------  -- rom_read  ------------------------------------------------------------------------------   p_read : process (clk, reset, rom_adr_i) variable v_loop : integer range 0 to 65536;  variable v_line : line; variable v_rom_data : rom_type; file f_initfile : text is in c_init_file;  begin if (not s_init) then  v_loop := 0;  while ((not endfile(f_initfile) and (v_loop < 65536))) loop   readline(f_initfile,v_line);  read(v_line,v_rom_data(v_loop));  v_loop := v_loop + 1;  end loop;  s_init <= true; end if;  if (clk'event and (clk = '1')) then -- rising clock edge  rom_data_o <= to_stdlogicvector(v_rom_data(conv_integer(unsigned (rom_adr_i)))); end if; end process p_read;   end sim;  The error statement from Quartus II is :  "error: vhdl loop statement error at mc8051_rom.vhd(103): loop must terminate at or before 10000 iterations"  Can anybody help me solve this problem?Thanx very much.

[Altera_Forum]

I think the message is straightforward, that a loop must terminate before 10,000, while you have 65,536.  

 Where is this error coming from, Quartus? Is this code supposed to simulate or synthesize? If it's for simulation, then it would run in Modelsim. If you wanted to synthesize this, my guess is that this doesn't synthesize to a counter. (The endfile command looks like a simulation construct, unless you have some hardware for this?)  If you really want to synthesize a counter for reading, then make a signal that is the correct number of bits and just have it increment on each clock.

[Altera_Forum]

i want to simulate it. but before simulating it in Quartus II, i must compile it first, right? 

because of that error, the compilation could not be completed.   i tried to solve the problem by creating 8 while-loops with each loop consists of iteration less than 10000. The following is the vhdl-codes:   if (not s_init) then  v_loop := 0;  while (v_loop < 8000) loop   readline(f_initfile,v_line);  read(v_line,v_rom_data(v_loop));  v_loop := v_loop + 1;   end loop;  v_loop := 8000;  while (v_loop < 16000 ) loop  readline(f_initfile,v_line);  read(v_line,v_rom_data(v_loop));  v_loop := v_loop + 1;   end loop;  v_loop := 16000;  while (v_loop < 24000 ) loop  readline(f_initfile,v_line);  read(v_line,v_rom_data(v_loop));  v_loop := v_loop + 1;   end loop;  v_loop := 24000;  while (v_loop < 32000 ) loop  readline(f_initfile,v_line);  read(v_line,v_rom_data(v_loop));  v_loop := v_loop + 1;   end loop;  v_loop := 32000;  while (v_loop < 40000 ) loop  readline(f_initfile,v_line);  read(v_line,v_rom_data(v_loop));  v_loop := v_loop + 1;   end loop;  v_loop := 40000;  while (v_loop < 48000 ) loop  readline(f_initfile,v_line);  read(v_line,v_rom_data(v_loop));  v_loop := v_loop + 1;   end loop;  v_loop := 48000;  while (v_loop < 56000 ) loop  readline(f_initfile,v_line);  read(v_line,v_rom_data(v_loop));  v_loop := v_loop + 1;   end loop;  v_loop := 56000;  while (v_loop < 64000 ) loop  readline(f_initfile,v_line);  read(v_line,v_rom_data(v_loop));  v_loop := v_loop + 1;   end loop;  v_loop := 64000;  while ((not endfile(f_initfile) and (v_loop < 65535)) loop   readline(f_initfile,v_line);  read(v_line,v_rom_data(v_loop));  v_loop := v_loop + 1;  end loop;  s_init <= true;  end if;  but then i got the error statement:  "error: vhdl error at mc8051_rom.vhd(153): index value 65536 is outside the range (65535 downto 0) of object "v_rom_data""  what should i do next?

[Altera_Forum]

Make sure you read the handbook on Moedlsim: 

http://www.altera.com/literature/hb/qts/qts_qii53001.pdf  There are two flows: 1) Functional simulation, which is probably what you want to do(many designers just do functional sims and static timing analysis). With functional simulation, all the code is directly read into Modelsim and Quartus does not need to be called.  2) Timing simulation. This is where you synthesize your design into a part and then export HDL files(a .vho or .vo) and a timing file(.sdo). These are then read into Modelsim. But your testbench still goes into Modelsim directly and does not get used by Quartus.  For the record, your while loop is probably getting synthesized into a state-machine or something, which is basically tens of thousands of states, which basically will be a huge number of gates, which is what you do not want.

[Altera_Forum]

does that mean that my program not be compiled in Quartus II? 

my prof ask me to simulate the program using only altera quartus.

[Altera_Forum]

You're going to be using the Quartus simulator, in which you draw a waveform as the input. (You can have it auto-count, which might be all you need). But your testbench would actually get synthesized into hardware, whether you want it to or not. Modelsim(or other 3rd party simulators) are for simulating testbenches.

[Altera_Forum]

We can modify/update the record data of a form by looping through its records. So, we are generally following the below code to do the same. 

       // loop through the records     var count = 1;   var maxCount = controller.getMaxRecordIndex();   for(var count=1; count<=maxCount; count++) {   // select the record   controller.setSelectedIndex(count);   /* Do any operations with the   selected record */   }  Hope this information is useful.Any suggestions are appreciated.