Honored Contributor II
09-14-2017 08:54 AM
hi all!I have a PCIe root complex (rc) based on Terasic Cyclone V GX board and system with PCIe endpoint (ep) on Cyclone V GT board. The RC side is managed by NiosII cpu, I tuned up altera linux pcie driver sources and wrote a simple enumeration recursive function. The system is being enumerated, and I set in downstream port on the rc side address base, limit, bus numbers. Finally I set command register with (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER) masks. On the rc side Nios write and read through PCIe HIP Txs port, on the ep side all devices managed through BAR0. I set adress translation tables (ATT) in both rc and ep. My goal is to allow ep send data itself without MSI and rc reading - so I set PCI_COMMAND_MASTER bit in rc downstream port PCIe command register. The data is sent by ep and goes from port RxM on the rc side. Then I connect ep through PCIe switch board based on XIO3130 (TI development kit). Nios cpu execute the same code, recursive enumeration works - the downstream port in RC and switch board as well as switch upstream port are initialized with the same values to the same registers. Parameters are set to the devices and can be read as well. the problem is: I see - data goes out from EP but data does't reach the RC. May be I need some advanced settings for ports of the switch... upstream port? Thanks in advance!!!