Procedure to add uClk_usr in Streaming DMA AFU

[Navaneeth]

I want to run my AFU in uClk_usr domain in the Streaming DMA AFU sample example. Please can you provide the steps that need to be followed in order to achieve this.

Thank you

[JohnT_Intel]

Hi,

Usually the AFU does not need to have a special SDC for it as it is covered in the default SDC.

[raks]

Hi,

I tried using uClk_usr with the help of clock crossing module. I instantiated the clock crossing module in the ccip_std_afu.sv  file and in spite of that, I got the "timing constraints not met" error.  What is the reason for getting that error and how to rectify it?

Thank you

[JohnT_Intel]

Hi,

Could you share with me the timing report or the compilation log?

[raks]

Hi,

Please find the attachment of the log files.

[Navaneeth]

Hi
Any reply is much appreciated.

[JohnT_Intel]

Hi,

I do not observed that the timing constrant error you mention in the logs provided.

[raks]

Hi,

The error can be seen in flame-job-script.sh.o891757 file. It is printed at the end of the file. 

[JohnT_Intel]

Hi,

You will need to try to recompile your design in different seeds to see if it is able to close the timing. May I know if the timing issue will impact your testing?

[Navaneeth]

Hi,

To reiterate the issue that we’re facing, it is that the timing constraints are not being met when we are synthesising our code using quartus for the purpose of getting the GBS file as output. The error files are attached in one of the previous messages.

We want to know how we can send a lower frequency of clock (user clock having 300 MHz) in the right manner to the avst decimator file so that we don’t get the timing constraints not met error.

We’re referring to the streaming dma afu bbb provided by Intel.

Thank you