Process Wait Statement

[Altera_Forum]

Please help me!!! I use Process Statement for my project, but have error: In Process Statement, we just have only one Wait untill??? It is wrong or right??? please help me. Thanhks a lot. 

  process  constant MAX:integer := 10;  variable x, y1: integer; begin y1 := 0; wait until (clk'event and clk = '1'); while (y1 < MAX) loop wait until (clk'event and clk = '1'); x := y1 ; y1 := y1 + 1; end loop; end process;  Error (10398): VHDL Process Statement error at ex_or.vhd(19): Process Statement must contain only one Wait Statement Error: Can't elaborate top-level user hierarchy Error: Quartus II Analysis & Synthesis was unsuccessful. 2 errors, 1 warning  Error: Peak virtual memory: 176 megabytes  Error: Processing ended: Mon Jan 19 21:36:24 2009  Error: Elapsed time: 00:00:02  Error: Total CPU time (on all processors): 00:00:02 Error: Quartus II Full Compilation was unsuccessful. 4 errors, 1 warning

[Altera_Forum]

Hi, 

 the code you provided is'nt synthesizable at all; it seems like you try to synthesize a bevahioural model for simulation.  the correct process would include a sensitivity list with asynchronous reset and the clock input like  MyStateReg : process (inResetAsync, iClk) is begin  if inResetAsync = cnAcivated then  elsif rising_edge(iClk) then  -- here is your stuff  end if; end process;  However, I would recommend using the 2 process method as proposed by Gaisler (Gaisler Research) to keep your design readble, servicable and 100% synthesizable.  regards, lestard

[Altera_Forum]

In order to be synthesisable a process can only contain one wait statement - yours contains two.  

 Lestard's template is the one I would use.  Also loops aren't always synthesisable - think about the logic that you're trying to synthesise not just the behaviour!

[Altera_Forum]

it's also worth looking at the templates in Quartus. 

 Open a VHDL file then Edit menu->Insert Template  and take a look at some of the code produced

[Altera_Forum]

No exactly for my problem!!! Please help me!!! 

This code I copy from book, which illustrates about "wait untill", i dont know what wrong???

[Altera_Forum]

Hi there, 

 no offence but please get a book about VHDL, a students guide to VHDL or whatever (see Amazon: Ashenden => A Designer's Guide to VHDL) and get at least familiar with the basic concepts of VHDL and writing synthesizable code. You should also become familiar with the basics of FSMs and FSMDs!  kind regards, lestard

[Altera_Forum]

This is the difference between synthesisable code and compilable behavioural code. 

 The code you have posted is perfectly legal VHDL and should compile in a simulator fine. You could, for example, use this in a testbench.  However, synthesisable code is a much smaller subset of the VHDL language and includes only code that corresponds exactly to gates and registers.  Your book isn't necessarily giving you code that is synthesisable! Quartus is giving an error because it is trying to synthesise your code.  This site is a good introduction to VHDL:  http://www.doulos.com/knowhow/vhdl_designers_guide/

[Altera_Forum]

--- Quote Start ---  No exactly for my problem!!! Please help me!!! This code I copy from book, which illustrates about "wait until", i don't know what wrong???  --- Quote End ---    There is nothing wrong with the code but wait statements are non-synthesizable . i.e. to quote wikipedia...  "A large subset of VHDL cannot be translated into hardware. This subset is known as the non-synthesizable or the simulation-only subset of VHDL and can only be used for prototyping, simulation and debugging."  i.e. as others have already state your code is fine for test-benches and simulation but cannot be turned into logic for an FPGA.  Take a look at this page  http://www.asic-world.com/vhdl/  Maybe it will help clarify some of the difference between RTL code than can be synthesized and behavioral code (like yours) that is OK for test-benches

[Altera_Forum]

Thanks a lot! 

I will remake. Thanks for ur help

[Altera_Forum]

The code provided by lizhi0007 should be synthesizable according to IEEE Standard 1076.6 - Standard for VHDL Register Transfer Level (RTL) Synthesis. 

 There are many rules that must be abided to for a wait statement to be synthesizable. However, it is incorrect to simply state that such statements are not synthesizable.  The most notable rule is that all the wait statements in a process (yes, there can be more than one) must specify the same edge of a single clock for the process to be synthesizable. This technique is used to specify "implict finite state machines".  Here is an example, extracted from IEEE 1076.6, of a process with multiple wait statements that should be synthesizable:  library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; Entity Mult is port( clk : in std_logic; start : in std_logic; done : out std_logic; A, B : in unsigned(3 downto 0); Y : out unsigned(7 downto 0) ); end Mult; Architecture ImplicitFSM of Mult is signal intY : unsigned(7 downto 0); begin MultProc : process begin wait until clk = '1'; if start = '1' then done <= '0'; intY <= (others => '0'); for i in A'range loop wait until clk = '1'; if A(i) = '1' then intY <= (intY(6 downto 0) & '0') + B; else intY <= (intY(6 downto 0) & '0'); end if; end loop; done <= '1'; end if; end process; Y <= intY; -- final state Y = A * B end;   I wonder when Quartus will support that?