Program Multiple FPGA

[Altera_Forum]

Can someone point me to an APP Note that describes how to compile multiple sof or pof files to generate a single file that can be used in Active serial mode to configure 3 FPGAs using the USB blaster an EPCS16 configuration device

[Altera_Forum]

you normally generate a pof or sof for each ppga an then tell the programmer which chip to load which sof or pof. I never heard of one pof/sof for multiple devices

[Altera_Forum]

--- Quote Start ---  you normally generate a pof or sof for each ppga an then tell the programmer which chip to load which sof or pof. I never heard of one pof/sof for multiple devices  --- Quote End ---    I know that - however when I use Convert Programming Files - with three sof files for the three FPGAs - and generate a single POF file - the file contains 3 pages. Which page corresponds to which FPGA? Page 0 - First FPGA?   In MY system PIN nCEO on FPGA 1 is connected to nCE on FPGA 2.

[Altera_Forum]

hello. 

 > Which page corresponds to which FPGA? Page 0 - First FPGA?  > In MY system PIN nCEO on FPGA 1 is connected to nCE on FPGA 2. yes you are right. I have done this before.  you told us you have 3 pages, FPGA3's nCE is also connected to FPGA2's nCEO, right?  if number of pages that are contained in pof file does not match with number of FPGA, your configuration will not done correctly. you can check that by probing conf_done pin of each FPGA.  does it help you? bye   if your circuit is connected like this document on page 258 https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/cyclone-v/cv_5v2.pdf

[Altera_Forum]

--- Quote Start ---  hello.  > Which page corresponds to which FPGA? Page 0 - First FPGA?  > In MY system PIN nCEO on FPGA 1 is connected to nCE on FPGA 2. yes you are right. I have done this before.  you told us you have 3 pages, FPGA3's nCE is also connected to FPGA2's nCEO, right?  if number of pages that are contained in pof file does not match with number of FPGA, your configuration will not done correctly. you can check that by probing conf_done pin of each FPGA.  does it help you? bye   if your circuit is connected like this document on page 258 https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/cyclone-v/cv_5v2.pdf  --- Quote End ---      My circuit is connected as shown in:  https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/cyc/cyc_c51013.pdf  Page13-12  I have 3 pages  I have 3 FPGAs  FPGA 1 nCEO connected to FPGA 2 nCE  FPGA 2 nCEO connected to FPGA 3 nCE  FPGA 3 nCEO NOT CONNECTED.  MY QUESTION:  SHOULD PAGE 0 Contain the file for FPGA 1? SHOULD PAGE 1 Contain the file for FPGA 2? SHOULD PAGE 2 Contain the file for FPGA 3?  OR   Should it be the other way around?

[Altera_Forum]

When adding multiple sof files to a pof file, they go in the order they are in the JTAG chain. File 1 to first FPGA in the chain, etc.

[Altera_Forum]

hello, this is Akira. 

 I think I forgot one thing. you told me, you made 3 pages.  but my old project says, you make one sof-page. and add three files.  do you understand difference?  see attached file.

[Altera_Forum]

--- Quote Start ---  When adding multiple sof files to a pof file, they go in the order they are in the JTAG chain. File 1 to first FPGA in the chain, etc.  --- Quote End ---    Many Thanks - This answers all my queries.