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Altera_Forum
Honored Contributor I
1,892 Views

Progress failed and Synopsys design constraints File file not found and high temp

Hi friends, 

I bought a de0 nano SoC and I m new Fpga ,this is why I need to help to activate the device.like I cannot run a led .My problem first ,device is warming towards 50 C and after the compilation I have critical warning "Synopsys Design Constrains File filee not found: 'test.sdc'.A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints.without it , the compiler will not properly optimize the design " and when I try to download the program .I got failed ,I m labouring 2 days
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9 Replies
Altera_Forum
Honored Contributor I
438 Views

Please provide more information. 

Have you added test.sdc to the project?
Altera_Forum
Honored Contributor I
438 Views

 

--- Quote Start ---  

Please provide more information. 

Have you added test.sdc to the project? 

--- Quote End ---  

 

Yes I added it but failed
Altera_Forum
Honored Contributor I
438 Views

How information do you want ,I am new because of I dont know

Altera_Forum
Honored Contributor I
438 Views

Your question is very vague, along the lines of : My project is not working - what is wrong with it. 

 

WHat is in the sdc file? what code are you using? why not post the code that has problems?
Altera_Forum
Honored Contributor I
438 Views

I'm using DE0 nano SoC board and I initiated the device as board(I mean as a new project -I didn't choose Cyclone V because Pin assignments are ready like this) ,and I got some warning and critical warning following below 

 

 

Critical Warning (169085): No exact pin location assignment(s) for 3 pins of 17 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report. 

 

Critical Warning (332012): Synopsys Design Constraints File file not found: 'asd.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. 

 

and my simple starter level codes 

 

module de0_nano_soc_baseline( 

 

 

//////////// CLOCK ////////// 

input FPGA_CLK_50, 

input FPGA_CLK2_50, 

input FPGA_CLK3_50, 

 

`ifdef enable_ADC 

//////////// ADC ////////// 

/* 3.3-V LVTTL */ 

output ADC_CONVST, 

output ADC_SCLK, 

output ADC_SDI, 

input ADC_SDO, 

`endif 

 

`ifdef enable_ARDUINO 

//////////// ARDUINO //////////// 

/* 3.3-V LVTTL */ 

inout [15:0] ARDUINO_IO, 

inout ARDUINO_RESET_N, 

`endif 

 

`ifdef enable_GPIO0 

//////////// GPIO 0 //////////// 

/* 3.3-V LVTTL */ 

inout [35:0] GPIO_0, 

`endif 

 

`ifdef enable_GPIO1  

//////////// GPIO 1 //////////// 

/* 3.3-V LVTTL */ 

inout [35:0] GPIO_1, 

`endif 

 

`ifdef enable_HPS 

//////////// HPS ////////// 

/* 3.3-V LVTTL */ 

inout HPS_CONV_USB_N, 

 

/* SSTL-15 Class I */ 

output [14:0] HPS_DDR3_ADDR, 

output [2:0] HPS_DDR3_BA, 

output HPS_DDR3_CAS_N, 

output HPS_DDR3_CKE, 

output HPS_DDR3_CS_N, 

output [3:0] HPS_DDR3_DM, 

inout [31:0] HPS_DDR3_DQ, 

output HPS_DDR3_ODT, 

output HPS_DDR3_RAS_N, 

output HPS_DDR3_RESET_N, 

input HPS_DDR3_RZQ, 

output HPS_DDR3_WE_N, 

/* DIFFERENTIAL 1.5-V SSTL CLASS I */ 

output HPS_DDR3_CK_N, 

output HPS_DDR3_CK_P, 

inout [3:0] HPS_DDR3_DQS_N, 

inout [3:0] HPS_DDR3_DQS_P, 

 

/* 3.3-V LVTTL */ 

output HPS_ENET_GTX_CLK, 

inout HPS_ENET_INT_N, 

output HPS_ENET_MDC, 

inout HPS_ENET_MDIO, 

input HPS_ENET_RX_CLK, 

input [3:0] HPS_ENET_RX_DATA, 

input HPS_ENET_RX_DV, 

output [3:0] HPS_ENET_TX_DATA, 

output HPS_ENET_TX_EN, 

inout HPS_GSENSOR_INT, 

inout HPS_I2C0_SCLK, 

inout HPS_I2C0_SDAT, 

inout HPS_I2C1_SCLK, 

inout HPS_I2C1_SDAT, 

inout HPS_KEY, 

inout HPS_LED, 

inout HPS_LTC_GPIO, 

output HPS_SD_CLK, 

inout HPS_SD_CMD, 

inout [3:0] HPS_SD_DATA, 

output HPS_SPIM_CLK, 

input HPS_SPIM_MISO, 

output HPS_SPIM_MOSI, 

inout HPS_SPIM_SS, 

input HPS_UART_RX, 

output HPS_UART_TX, 

input HPS_USB_CLKOUT, 

inout [7:0] HPS_USB_DATA, 

input HPS_USB_DIR, 

input HPS_USB_NXT, 

output HPS_USB_STP, 

`endif 

 

//////////// KEY //////////// 

/* 3.3-V LVTTL */ 

input [1:0] KEY, 

 

//////////// LED //////////// 

/* 3.3-V LVTTL */ 

output [7:0] LED, 

 

//////////// SW //////////// 

/* 3.3-V LVTTL */ 

input [3:0] SW 

 

); 

 

abc abc1(SW[0],SW[1],LED[0]); 

 

endmodule 

 

 

 

module abc(input a,b,output q); 

 

and u1(q,a,b); 

 

endmodule 

 

 

When I tried upload codes in device ,I got (Failed) situation to progress.I'm spending my time with it for a few day and I'm tired 

 

Thanks for helps
Altera_Forum
Honored Contributor I
438 Views

Also When device is working with the program that loaded in it ,temperature about 50 C , is it normal?

Altera_Forum
Honored Contributor I
438 Views

 

--- Quote Start ---  

 

Critical Warning (169085): No exact pin location assignment(s) for 3 pins of 17 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report. 

 

--- Quote End ---  

 

 

This means that some pins in your code dont have an assignment to a physical pin on the device, so the compiler has ramomly assigned them for you (probably completly wrongly) 

 

 

--- Quote Start ---  

 

Critical Warning (332012): Synopsys Design Constraints File file not found: 'asd.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. 

 

--- Quote End ---  

 

 

This means the asd.sdc file does not exist where you said it does - you probably have the path wrong. 

 

As for running at 50degrees - if you have no heat sink on it, the probably.
Altera_Forum
Honored Contributor I
438 Views

Problem is solved ,so simple ,programmer->autodetect and choose which device that is used and double click device and choose .sof file and ready

Altera_Forum
Honored Contributor I
438 Views

But device still 50 centigrade

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