Re: Proper Constraints Clock Enable Multicycle

Altera_Forum · ‎06-11-2011

Hello all, I'm new to Altera devices and the Quartus software. I had a quick question about multicycle constraints for clock-enables.

My clocking architecture is pretty simple. I have a 50MHz oscillator input to the FPGA. This oscillator drives an internal PLL which in turn generates a 21.4286MHz system clock.

The 21.4286MHz system clock which is connected to the clock input of every register in the entire FPGA. This system clock is also used to generate 2 clock-enable signals (called clk_en_module1 and clk_en_module2):

The first clock-enable is connected to the enable pin of all registers in a sub-module called "module1" in order to create an effective clock-rate of 21.4286M / 12 = 1.79MHz.
The second clock-enable is connected to the enable pin of all registers in a sub-module called "module2" in order to create an effective clock-rate of 21.4286M / 4 = 5.36MHz.

Here are my constraints:

# 50MHz Input Clock (Oscillator)# #  This clock only drives the internal PLL
create_clock -period 20.000 
# Add clock constraint for (50M*3/7) = 21.4286MHz system clock# This clock is used to generate the 2 clock-enables used by the rest of the system.
create_generated_clock -name sys_clk 
  -source }] 
  -duty_cycle 50.000 -multiply_by 3 -divide_by 7 -master_clock {i_board_osc_0} 
  }]
# Add multicycle exceptions on all paths to registers controlled by Module1's clock-enable# Module1's clock-enable results in an *effective* clock rate of (sys_clk/12) = ~1.79MHz
set_multicycle_path -setup 12 
  -to  
  -through ]
# Add multicycle exceptions on all paths to registers controlled by Module2's clock-enable# Module1's clock-enable results in an *effective* clock rate of (sys_clk/4) = ~5.36MHz
set_multicycle_path -setup 4 
  -to  
  -through ]

I must be doing something very wrong though because if I use the above multicycle constraints I get insane timing errors (e.g. -321428ns slack). And if I comment out just the multicycle constraints I meet timing just fine. Does someone know what I'm doing wrong? I would appreciate any help.

Thanks!

Jonathon

Altera_Forum · ‎06-14-2011

Hi.

Try to add this:


set_multicycle_path -hold 11 
-to  
-through ]
set_multicycle_path -hold 3 
-to  
-through ]

Altera_Forum · ‎06-14-2011

Dude!! That totally worked!! Thank you so much!! Not only did those constraints work but it makes perfect sense why they worked. I was moving the setup time forward but was neglecting to also move the hold time forward.

THANKS AGAIN! :)