Hi all:
I am using QDR II + IP core of ALTERA, but the IP can't work correctly. I test the core in my customized board with quartus II 12.0 SP2(windows XP sp3) and find some results:
1. The device in board is:1)FPGA:5SGXEA7K2F40C2 2)18x4M QDRII+: CY7C25632KV18-450BZC; 36x2M QDRII+: CY7C25652KV18-450BZC;
2. Test the IP with CY7C25632KV18(reference clock: 100Mhz, memory interface clock: 400Mhz, application interface speed: half or full) , I write some data to it and then read back ,the data is correctly;
3. Test the IP with CY7C25652KV18(reference clock: 100Mhz, memory interface clock: 400Mhz, application interface speed: half) , I write some data to it and then read back ,the data is correct;
4. Test the IP with CY7C25652KV18(reference clock: 100Mhz, memory interface clock: 400Mhz, application interface speed: full) , I write some data to it and then read back ,the data is incorrect;
5. Test the IP with CY7C25652KV18(reference clock: 100Mhz, memory interface clock: 200Mhz, application interface speed: full) , I write some data to it and then read back ,the data is incorrect;
If the memory clock speed of core is the same when the application interface speed is full and half, I think the PCB is good with 3 of above.
Why the core can't work correctly when operation with full speed of 36 bit QDRII+?
Can Someone help me? Thanks!
