Qsys SDRAM wire export, clk missing

[Altera_Forum]

Hi All, 

  This is a newbie question.  I don’t have much luck adding SDRAM to my project. I’ve completed the “Nios II Hardware Development Tutorial” and the first count binary demo is working as expected on the DE0 using onchip memory.   When I added SDRAM to the project it didn’t work to troubleshoot my problem I’ve changed the linker memory regions in BSP editor so now sdram_0 is only used by the heap. The demo is working again and to verify SDRAM I’m using malloc() to print a string. The malloc() is working if the linker memory is pointed to onchip mem. I’m just using malloc to check SDRAM.    I’m confused by the qsys implementation of SDRAM export wire. There is no CLK among the export wires (wire_export.jpg)    However PIN E5 supposed to be connected to DRAM_CLK.(de0_doc.jpg) Because of this DRAM_CLK is not shown in pin planner so I cannot connect it.  There may be other problems but I assume this is a blocking one.  The DE0 examples are based on SOPC Builder but I’d like to use Qsys. (qsys_contents.jpg)       Qsys contents looks like this:    Thanks,  James

[Altera_Forum]

I don't know anything about that board but you most likely need to either create another PLL output for the SDRAM and export it or add a clock bridge component (under merlin components), wire up the c1 port of the PLL to the bridge input and export the output. Creating another PLL output is probably the easier way to do this especially if you plan on putting a phase shift on that exported clock.

[Altera_Forum]

[edit] 

Actually you can ignore my post below. DRAM_ADDR[12] in connected to NC on the schematics so it is not used. Anyone could share a simple SDRAM template for qsys?    Thanks for responding. Not connecting the clock was definitely a problem.   I was studying the sample projects provided by Terasic (DE0 board) . I’ve modified the core from Nios/f to Nios/e in the SOPC sample project and I was able read and write to SDRAM. This is great but Terasic only provides SOPC and not Qsys examples. I’d like to build my project from scratch with Qsys. The two is quite different and I cannot figure out what I’m doing wrong with Qsys. I’ve copied the timing values from SOPC but there seems to be a problem with the Data and Address PIN assignments. DRAM_ADDR[12] the last PIN in the Terasic example is not showing up in Qsys.  I’ve attached Qsys wire exports to my previous post.     SPOC Sample Project: (where all pins are correct)  /////////////////////// SDRAM Interface ////////////////////////  inout [15:0] DRAM_DQ; // SDRAM Data bus 16 Bits  output [12:0] DRAM_ADDR; // SDRAM Address bus 13 Bits  output DRAM_LDQM; // SDRAM Low-byte Data Mask  output DRAM_UDQM; // SDRAM High-byte Data Mask  output DRAM_WE_N; // SDRAM Write Enable  output DRAM_CAS_N; // SDRAM Column Address Strobe  output DRAM_RAS_N; // SDRAM Row Address Strobe  output DRAM_CS_N; // SDRAM Chip Select  output DRAM_BA_0; // SDRAM Bank Address 0  output DRAM_BA_1; // SDRAM Bank Address 1  output DRAM_CLK; // SDRAM Clock  output DRAM_CKE; // SDRAM Clock Enable    Is there any way to change the wire assignment in Qsys? Of course I could just use SPOC and forget about Qsys…    Thanks,  James

[Altera_Forum]

Are you sure you parameterized the memory controller the same way as before? Qsys is just exporting the wires/buses it sees coming from the SDRAM controller so if you have a mismatch that effects the addressing I would expect the behavior you are seeing.

[Altera_Forum]

Well I gave up on Qsys. I couldn't figure out what I was doing wrong. I think I've checked everything.  

I've built a basic project with SDRAM from scratch using SOPC and it worked for the first try. I can read/write to my SDRAM. strange.  I've learned lot during troubleshooting though.  Thank you for helping.

[Altera_Forum]

Hi, I have exactly the same problem right now. Is there a solution in the meantime without changing to SPOC Builder?

[Altera_Forum]

I couldn't figure it out with QSYS. Mind you I didn't try it on 11 SP 1. 

I've switched to SOPC.

[Altera_Forum]

Ok, I got it. At first it's not an error of Qsys not wiring out the SDRAM Clock. 

The User has to export an own clock signal in Qsys, i.e. from the PLL, for the SDRAM Clock. Doing this you will recognize the signal/wire in Quartus Pin Planner and you can root it to the specific FPGA Pin. My whole system works fine now.

[Altera_Forum]

Another reason I switched to SOPC was that when I modified the design and tried to update the schematics in Quartus the PINs got shuffled around this didn’t happen with SOPC. Do you see the same issue?

[Altera_Forum]

Hi, no I had no "pin-shuffling". I use the Qsys version comming with Quartus11 Sp1 at the moment.