Hi , I am trying to create a new component on Qsys using my verilog code in quartus. I am getting some errors [please look over the attachment], I don`t know how to fix it. Please guide me
Verilog code
module coun (
LED , // Output of the counter
clk , // clock Input
);
input clk;
output reg LED;
reg out=0;
always @(posedge clk) begin
out <= out + 1;
LED=out;
end
endmodule I need step-step training please
