Quartus reverses functions of AND and OR gates

[Altera_Forum]

I am using the schematic/block editor to put an AND gate into a .bdf file and run it on a Nios Cyclone devkit and getting the wrong result. 

 Two input pins from pushbuttons --> AND Gate --> inverter --> Output pin to LEDThe inverter is required for this board to make the LED turn on for a logic high. I assigned the pins, compiled, and programmed it into the FPGA.  The AND gate acts like an OR gate. If I put in an OR gate, I really get an AND. NAND behaves like NOR, etc.  The same thing happens with files generated in Quartus II 9.0 on Linux and 9.1SP1 on Windows XP (both the web editions).  Anyone know what's going on?

[Altera_Forum]

Assuming you are talking about the Cyclone (one) Nios dev kit the push buttons are active low (they have pull ups) and the LEDs are active high (they have pull downs). 

 So your logic should be:  assign led = (!pin[0]) & (!pin[1]);  or this using that law I learned in school but can't remember what it's called :)  assign led = !(pin[0] | pin[0]);

[Altera_Forum]

Thanks! That's exactly what it was. Just proves that the simplest explanation is usually the correct one. :)

[Altera_Forum]

--- Quote Start ---  that law I learned in school but can't remember what it's called :)  --- Quote End ---   That would be de morgan's law (http://en.wikipedia.org/wiki/de_morgan%27s_laws).

[Altera_Forum]

occam's razor (http://en.wikipedia.org/wiki/occam%27s_razor) could be applied here as well. :)