Question about Monitor

[Altera_Forum]

Hello, 

 is it possible to synthesize the "monitors" on the altera fpgas'. There are Monitor IPs such as Avalon MM Monitor. Can I synthesize such "Monitors"?

[Altera_Forum]

--- Quote Start ---    Will I have to write some test programs or modify any generated codes to simulate my design [writing data to the RAM].   --- Quote End ---  Yes. You will have to generate Avalon-MM BFM transactions to write to an address that corresponds first to the PCIe master interface so that a PCIe write transaction is generated, that write transaction should then be accepted by the target interface on the second design (BAR0 access), and then that should translate to an Avalon-MM transaction to your RAM internal to the second design.    --- Quote Start ---    Is this an hierarchy system design example? [first you create a PCIe BFM, and then save that system and then connect that system to the RAM (second system)]   --- Quote End ---  There is no hierarchy here; they are two completely separate designs (two separately named Qsys designs). A hierarchical design is one in which you define a Qsys component as a collection of Avalon components, and leave top-level Avalon connections, so that the new component can be dropped into an Avalon system. The components you are to design have PCIe ports at the top-level. You will connect them in the testbench, but you would not use these components in a Qsys hierarchy.    --- Quote Start ---    I am curious, how long have you been working with Quartus you have a good working knowledge about it. [I started 3 weeks ago]   --- Quote End ---  Quite a few years.  Cheers, Dave

[Altera_Forum]

that write transaction should then be accepted by the target interface on the second design (bar0 access) 

 Isn't this in the first design itself? the second design is only the RAM right? I think my thinking is restricted to what I have been thinking all these days. Please explain everything explicitly, I think I have misunderstood some of the stuff.  Thanks

[Altera_Forum]

--- Quote Start ---   Please explain everything explicitly, I think I have misunderstood some of the stuff.   --- Quote End ---  I've drawn a picture. Print it out, and re-read my previous posts. Hopefully it will become clearer. Note that you might have to add other Avalon-MM interfaces onto the PCI/PCIe core simply so that you can set it up correctly. I have not used the core, so cannot tell you.  The main purpose of the picture is to show you the major components you need to design, and it shows you the data path that your testbench will be testing. The key thing for you to understand is that this testbench is to test the blue component on the right; this is the component you synthesize into hardware, while everything else is simply test code for simulation.  Cheers, Dave

[Altera_Forum]

Thanks, this will be my mini project for the next few days

[Altera_Forum]

Good Morning Dave, 

 Can I email you the screen shots to your email id. I cannot attach them in here because they are too big.  Thanks, Aditya

[Altera_Forum]

--- Quote Start ---   Can I email you the screen shots to your email id. I cannot attach them in here because they are too big.   --- Quote End ---  Sure, that is fine.  Cheers, Dave

[Altera_Forum]

Hello Dave, 

 I am not able to initialize the RAM memory locations. I could do this in SOPC, but in Qsys I am not able to do it.  Do you what the problem might be? The name of the memory file is consistent everywhere.  Thanks, Aditya

[Altera_Forum]

Hello Dave, 

 Sorry for asking such a simple question. I got it!  Thanks, Aditya

[Altera_Forum]

Hello Dave, 

 Is it okay to leave the pcie_core_clock and pcie_core_reset floating ?   Thanks, Aditya

[Altera_Forum]

--- Quote Start ---   Is it okay to leave the pcie_core_clock and pcie_core_reset floating ?    --- Quote End ---  No! How would you expect the core to work if it does not have a clock and reset?  Cheers, Dave

[Altera_Forum]

Good Morning Dave, 

 I am talking about the outputs. The pcie_core_clock and pcie_core_reset are the outputs form the PCIe IP core.  Thanks, Aditya

[Altera_Forum]

--- Quote Start ---   I am talking about the outputs. The pcie_core_clock and pcie_core_reset are the outputs form the PCIe IP core.   --- Quote End ---  Are they outputs from the 'root complex' (your BFM design) or from the 'end-point device' (your FPGA design).  The reference clock from the root complex might be required by the end-point device if the two are to be synchronous ... or that same connection could be via a common clock in your testbench. I would look at Altera's examples to see what they do.  This webcast implies that Altera's examples have a PCIe BFM  http://www.altera.com/education/webcasts/all/source-files/wc-2011-pcie-technology-design-fpga/player.html  Earlier you implied that Altera did not.  Setting up the testbench I have described is a good exercise in learning the tools. Once you've got it working, you should go back and check out the newest Altera PCIe examples ... perhaps they have improved.  Cheers, Dave

[Altera_Forum]

Hello Dave, 

 They are the outputs of the 'Root Port'. The 'End Point' also has the clock and the reset output. I have added two PCIe IPs in my qsys system [one for the BFM and other for the DUT] Also, when I connect the corresponding conduits[between the BFMs and the DUT] together I get errors [error increases as I connect the conduits together]  Thanks, Aditya

[Altera_Forum]

Hello Dave, 

 What exactly does a PCIe IP inside a FPGA do? PCIe is a bus and let us assume that one of the devices connected to the bus is FPGA.   The signals from the PCIe bus enter the PCIe IP inside FPGA and then the signals enter the avalon fabric and then the RAM right?   Thanks, Aditya

[Altera_Forum]

--- Quote Start ---   What exactly does a PCIe IP inside a FPGA do?   --- Quote End ---  If you do not understand PCIe at this level, then you need to listen to the Altera webinar's before attempting to simulate a system containing them.  PCIe is a specification that involves an electrical interface (the high-speed SERDES lanes), and a configuration/programming interface (borrowed from the PCI specification).  The FPGA IP core implements the physical interface using its SERDES channels, and Altera has implemented the configuration interface. Your designs can add custom functions to the BAR regions. The root complex version of the IP core needs to 'setup' the PCIe bus. The BIOS or Bootloader running on the device with the root complex would go out and 'enumerate' the PCIe bus, i.e., find all the devices and give them base addresses in the memory map of the root complex. The FPGA IP configured as end-points respond to the root complex with details about what they require in terms of resources on the PCIe bus.  If you do not understand the details of this, then you will not be able to get your simulation working, since your testbench code has to perform the functions of the BIOS/Bootloader to configure the PCIe bus before you can issue transactions.    --- Quote Start ---   The signals from the PCIe bus enter the PCIe IP inside FPGA and then the signals enter the avalon fabric and then the RAM right?   --- Quote End ---  According to the webinar link I posted you, the PCIe IP can implement an Avalon-ST interface where you see transaction packets, and you have to write code for it, or it can implement a simple Avalon-MM master. In your case, it sounds like you are using the IP configured as an Avalon-MM master, which in turn connects to the RAM.  What is happening at the system level is you issue a high-level command from your fake host system, eg. a read, which in C code could be the dereferencing of a pointer, that read targets the PCIe root complex, which converts it into a PCIe packet destined for your end-point. The end-point captures the PCIe packet, converts it back into a read command, issues that read as an Avalon-MM master, and captures the read data. The PCIe core in the end-point then converts the read data into a PCIe packet, sends it back to the root-complex, the root-complex converts it back to a data value to return as read data. Its all very complicated :) Its even trickier if you look at a Qsys system, given that the transactions between masters and slaves are also converted into packets, but this time Qsys packets.  Cheers, Dave

[Altera_Forum]

Thanks a lot Dave. I think I know what the IP's are doing [they do the signal translation to PCIe standard between the end point and the root port]. I too want to understand things in depth, its more fun. 

 In your design you have two PCIe IPs. How do you connect those IP's, I connected the conduits together. I get errors.  Thanks, Aditya

[Altera_Forum]

--- Quote Start ---  I kind of understand what you are talking about, but I haven't understood things as deeply as you have. I want to understand things in depth, its more fun.   --- Quote End ---  My comments should be taken as encouragement to learn more. The Altera webinars are pretty good, so go and look at their online training and listen to a few of them.    --- Quote Start ---   In your design you have two PCIe IPs. How do you connect those IP's, I connected the conduits together. I get errors.   --- Quote End ---  The PCIe IPs should be connected exactly as you would on a PCB.  The SERDES links would connect as; root_tx => endpoint_rx, and root_rx <= endpoint_tx.   What other signals are there?  Cheers, Dave

[Altera_Forum]

Hello Dave, 

 Oh yes, I am taking your comments in a positive way:-P. I will look at the webinars. I will email you an image of the PCIe IP. When I click on edit how do I configure the IP to be root port or end point port. [in qsys]  thanks, Aditya

[Altera_Forum]

--- Quote Start ---  When I click on edit how do I configure the IP to be root port or end point port. [in qsys]   --- Quote End ---  Sorry, I have not used this IP. The IP users guide and examples should tell you how to do it. The PCIe webinar indicated the component could be configured for both root complex and end point, so the feature exists.   Perhaps try this webinar: http://www.altera.com/education/training/courses/opci1010  Here's the IP page: http://www.altera.com/products/ip/iup/pci-express/m-alt-pcie8.html  Did you happen to read this:    --- Quote Start ---   The PCI Express Compiler includes an endpoint testbench that incorporates a simple root-port bus functional model (BFM) and multiple endpoint example designs. You can use these example designs, available in clear-text source-code (VHDL) and Verilog (HDL), as references to kick-start your design, while the simple root-port BFM is geared to provide an "out of the box" PCI Express experience.   --- Quote End ---  The PCIe compiler includes a PCIe root complex BFM ... so technically you could have used that in your design.  The PCIe hard-IP page:  http://www.altera.com/technology/high_speed/protocols/pcie-hard-ip/pro-hard-ip.html  has these comments    --- Quote Start ---    Dual mode to support both endpoint (legacy and native) and root port functionality   --- Quote End ---  You need to read the documentation.  http://www.altera.com/literature/ug/ug_pci_express.pdf  Chapter 15 has testbench examples for both root and endpoints.  Cheers, Dave

[Altera_Forum]

Hi Dave, 

 Yes, even the video tutorial showed that PCIe can be configured as Native endpoint, root port and Legacy Endpoint [but this was done in the Mega Function Wizard]. When I edit the component in Qsys, those options don't show up!.   I will re-watch the video and look at the manual in detail.  Thanks, Aditya

[Altera_Forum]

--- Quote Start ---   Yes, even the video tutorial showed that PCIe can be configured as Native endpoint, root port and Legacy Endpoint [but this was done in the Mega Function Wizard]. When I edit the component in Qsys, those options don't show up!  --- Quote End ---  What you see in Qsys is defined by the _hw.tcl file for the IP component. Its quite possible Altera has not defined the Qsys view with all the features available from the MegaWizard component. If that is the case, then just use the MegaWizard to define the component, and from Qsys generate an _hw.tcl file that implements an Avalon-MM master interface that does not include it in the Qsys system. This will then result in a top-level Qsys design with master ports that you can externally connect to the PCIe block generated via the MegaWizard.  Cheers, Dave