Question on how Quartus II Synthesizes Circuit

[Altera_Forum]

Hi, 

 I have a couple of questions related to the way Quartus 2 is performing the synthesis of simple verilog programs.  I have notice that when I program simple verilog programs (just Boolean operation), the RTL viewer tool indicate that between two nets there is the presence of BUF (LCELL). Which means that if I have a wire called A and a wire called B, between A and B, there is this buffer (I guess in between). I also noticed that if I connect the HSMC connector and I want to output my Boolean operation on them there is a BUF (DIRECT).  So here are my questions: 1) What are those BUF (LCELL) and BUF (DIRECT) and what are they used for ? 2) Is it possible to bypass them (remove them from the synthesis, just to see what happen)?  3) If it is possible, how would you do it in Quartus II ?  Thank you for your help ! :)  Cheers. Pdoc

[Altera_Forum]

Can you post your Verilog? And what device are you targeting? 

I find it a bit weird you're seeing LCELL in RTL viewer..  Anyway,  The RTL viewer shows the high level interpretation the synthesis tools does of your code; it is not optimized. The tools then proceed to map what you see in the RTL viewer to FPGA resources, as efficiently as they can.

[Altera_Forum]

yes there are buf lcells sometimes. i think you have timing optimization option turned on inside synthesizer. i guess quartus tries to analyse if there is any need for time delay, and adds an lcell there to artificially generate time delay.lcells are like lava thing. lava is a base material that later generates various types of terrain.mountains valleys so on. lcells have property to transform into logic gates, registers,adders, multiplexers and so on. by adding pure lcell to circuit, it means that no useful operation is performed since lcell hadn't transformed into anything yet. but taking a signal through it takes time, and delays a signal.and quartus thinks that in your situation it is a useful thing. well, you should go in settings -> analysis and synthesis and disable timing driven synthesis checkbox. also go to fitter suboption and uncheck "optimise hold timing" . that should tell the synthesizer to not to think about timing correctness in the circuit.

[Altera_Forum]

Hey Ilik,  

Thank you very much for this piece of information, this is actually exactly what I was looking for !! I will try to make the changes you suggest. Thank you again for the help. Best, Pdoc.

[Altera_Forum]

few days ago i had such an interesting situation. i had a clock going into altera from a pin. i needed this clock to triggering something inside, but when i simulated it, triggered signal reacted the register with very big delay. it was obvious that such a big delay was not normal for altera. then i checked RTL viewer and noticed that synthesizer added buffer LCELL near the clock pin enterance, and this delayed my clock in phase. synthesizer also added one more disgusting LCELL buffer and named it myclock ~buf0clkctrl. and that lcell delayed my clock so much, that when my clock actually reached a register it had 180 degree phase shift with respect to original clock that came through input pin. why did this happened? i had a statement there, something like when my counter goes beyond number 5, then react on clock positive edge. synthesizer looked at my counter and noticed that clock edge nearly matches the point where the counter increments, and thus changes it's numerical value. as you may know these transition moments are very dangerous, in these picoseconds counter's true value is not unknown, and one must wait until it finishes incrementing and settles down with the new value. so synthesizer thought it would be nice to delay my clock to keep it's positive edge a little bit away from counter's transition point. thats why it added that horrible bufclkctrl which threw my clock in phase. unchecking timing analysis didnt helped. the buffer was still there. and thats what i did, i went into an assignment editor,chose Design Entity (display all) , searched the node under name ~buf0clkctrl. selected it and gave it an option Netlist Optimizations Never allow. and compiled the project. it instantly killed that buffer and my clock came back to it's original phase. but the threat remains, the one from which synthesizer was trying to save me. my clock positive edge is too close to my counter increment transition point. if something goes wrong and transition will get late... the system will collapse.  

whatever... at least i'v got my phase back :) in other words use this method i described to force synthesizer to kill synthesis time buffers