and dataflow and gate-level...Well I am sort of confident about some:
functional simulation sounds like simulation of functionality irrespective of how it is going to be implemented. It is used to mean time-less device-less simulation of your design functionality irrespective how it is finally mapped in the target.
behavioural: I only use that in the social text, but it is borrowed by vhdl people to mean those sequential constructs that describe say behaviour of a counter rather than designing it at lower level of gates and flips.
behavioural is used as one of 3 design approach levels:
structural level(instantiation)
dataflow level
behavioural
there is more, sorry, the lowest most is silicon level which is left to Altera foundries. I also prefer to add "others" level to indicate the poor miners who are always invisible in our daily life.
RTL was coined with standrds 1076 to indicate something else quite different, it relates to that safe design methodolgy now used in FPGAs by every sensible designer, it relies heavily on breaking up logic paths by clked registers. Warning: tutors tend to mix up between dataflow and RTL.
I leave the meaning of dataflow for you.
