RGMII RX Clock on a non-clock pin (normal pin)

[Altera_Forum]

Hi there, 

 I have some timing problems with my rgmii rx interface. Due to a design error the rx clock is not connect to an dedicated clock pin. This error results a high delay on clock path and the hold timing for the ddr input buffers can't be reach. The delay from the clock pin to the ddr buffer inside the fpga is nearly 4.5 ns, where the delay for the ddr input buffer is only 3.5ns.  Is there anyway to compensate the error aftwards? (through an IP-Core or an assignment maybe?)  Regards, Chris

[Altera_Forum]

--- Quote Start ---   Is there anyway to compensate the error aftwards? (through an IP-Core or an assignment maybe?)   --- Quote End ---   This is why you should place-and-route a design before the board is built :)  The two work-arounds I can think of are;  1. Add a rework wire to route the signal to a clock pin.  2. Use a PLL to phase-shift the clock so that you can meet timing.  Option (2) "sounds good", but since you have used a non-dedicated clock pin, you'll probably get warnings about that too. However, it might be enough for you to confirm that the RGMII interface works "well enough" so that you can move on and find any other hardware errors.  The long-term fix would require the board design be corrected, sorry.  Cheers, Dave

[Altera_Forum]

I use a Arria V fpga. The plls are only reachable from clock pins. With any other pin the fitter complains with an error....

[Altera_Forum]

--- Quote Start ---  I use a Arria V fpga. The plls are only reachable from clock pins. With any other pin the fitter complains with an error....  --- Quote End ---   Ok, I commented it might not be easy.  Does your FPGA have a clock input that is in common with your RGMII interface? If so, then you could use that for the PLL source, rather than the RX clock, and then you'd have to figure out the correct alignment to get things to work.  The best solution would be to try and wire the RX clock to a clock pin ... easier said than done on a multi-layer board ... but if your BGA balls have exposed vias, it would not be too impossible to solder a wire to both the PHY and FPGA ... but it might not be a particularly clean clock waveform.  Cheers, Dave

[Altera_Forum]

Thank you for your help Dave. 

 I thought about soldering a wire on a clock pin, but I haven't found one with a via on the ball, which isn't used... So we are reconsidering a redesign..  Cheers, Chris

[Altera_Forum]

--- Quote Start ---   I thought about soldering a wire on a clock pin, but I haven't found one with a via on the ball, which isn't used... So we are reconsidering a redesign..   --- Quote End ---   Keep in mind that since this hardware has one error, it may have others, so its important that you hack/chop/drill/cut as much as you can on this board to isolate all the issues.  So, if you do have another clock pin that is already used, and can remove that clock source for the purpose of this test, then go ahead and make that change (after testing whatever that clock source is used for, of course!).  Cheers, Dave

[Altera_Forum]

--- Quote Start ---  Hi there, Is there anyway to compensate the error aftwards? (through an IP-Core or an assignment maybe?)   --- Quote End ---    Hi,  I think this is not recommended way to implement it, but in principle You could try to use logic resources for the clock routing towards the DDRIO-cell. In this case it could be the shortest path, and quite well matched with data..   e.g. set_instance_assignment -name GLOBAL_SIGNAL OFF -to rx_clk  Then you should instantiate clkctrl -block to provide optimal clock for the rest of the domain.. Small design could work without clkctrl (at least design with only Altera TSE did meet timings without clkctrl). A bigger design that I tried failed without clkctrl,..   With Best Regards,  Jarkko  PS. This same feature can be found from Cyclone V GT FPGA Development Kit schematics :)