Inquiry Regarding Cyclone V IBIS Model Definitions and Updates

[RyusukeYOKOYA]

Dear Intel Support Team,

I hope this message finds you well.

I am currently conducting IBIS simulations for the Cyclone V FPGA, specifically for the part number 5CGXFC9C6F23, and I have a few questions regarding the IBIS model definitions provided on your official website.

Upon reviewing the IBIS file available at the following link:
https://www.intel.co.jp/content/www/jp/ja/support/programmable/support-resources/board-layout/ibs-ibis-index.html
I noticed that several I/O buffer models appear to have identical definitions despite having different names. For example:

• "lvcmos_rtpio_d2s1" and "lvcmos_rtpio_d16s1"
• "lvcmos_rtpio_d2s1_p" and "lvcmos_rtpio_d16s1_p"

These models seem to be completely identical in terms of their IBIS definitions, which raises concerns about their accuracy and applicability for simulation purposes.

I would like to ask the following:

1. Are there any updated or revised IBIS model files for Cyclone V released after March 20, 2020, which is the last modification date shown on the website?
2. Among the available models, which ones are considered accurate and appropriate for simulation, particularly for the I/O standards listed below?

The I/O standards I plan to use are:

• 3.3V LVCMOS (lvcmos_*)
• 3.3V LVTTL (lvttl_*)
• SSTL-135 (sstl135_*)
• Differential SSTL-135 (dsstl135_*)

Your guidance on this matter would be greatly appreciated, as it will help ensure the validity of our signal integrity simulations.

Thank you very much for your support.

Best regards,
Ryusuke YOKOYA

[AqidAyman_Intel]

Hello Ryusuke YOKOYA,

I'll check this and get back to you as soon as possible.

Regards,

Aqid

[RyusukeYOKOYA]

Hi Aqid,

Thanks for getting back to me.

I appreciate you looking into this, and I’ll wait to hear from you when you have more info. Looking forward to your update.

Best regards,

Ryusuke YOKOYA

[FvM]

Hi,
above post refers to IBIS models that don't exist in linked IBIS file, e.g. lvcmos_rtpio_d16s1. 3.3V LVCMOS doesn't support current strength above 2 mA.
Thus it's not clear what "identical definitions despite having different names" actually refers to? 

lvcmos_rtpio_d2s1 and lvcmos_rtpio_d2s1_p differ in activating the clamp diode.

[AqidAyman_Intel]

I checked cyclone5.ibs file and noticed that "lvcmos_rtpio_d16s1" and "lvcmos_rtpio_d16s1_p" is not listed in the ibis file.

According to the Cyclone5 IBIS Models UG, "lvcmos" refer to 3.3 V LVCMOS and according to the Cyclone V Device Handbook, 3.3 V LVCMOS supports current strength setting of 2mA only. So, this is confirmed that lvcmos models should not have "...d16.." because this refers to 16mA current strength.

[RyusukeYOKOYA]

Dear Aqid and FvM,

Thank you for your responses and clarifications.

I would like to correct my initial message. The example I meant to refer to was not:

• lvcmos_rtpio_d2s1 and lvcmos_rtpio_d16s1

but rather:

• lvcmos_rtpio_d2s1 and lvttl_rtpio_d16s1
• lvcmos_rtpio_d2s1_p and lvttl_rtpio_d16s1_p

Upon inspecting the IBIS file (cyclone5.ibs), I noticed that these pairs of models appear to have identical IBIS definitions, despite differing in name and intended I/O standard and drive strength. This raises concerns about whether the models are correctly differentiated and whether they can be reliably used for signal integrity simulations.

Could you please confirm whether this duplication is intentional, and if not, whether updated or corrected IBIS models are available?

Thank you again for your support.

Best regards,
Ryusuke YOKOYA

[FvM]

Hi,
thanks for correction. Now I get your point.

lvcmos_xxx_d2xx Ibis I/V curves don't look like 2 mA current strength, according to datasheet specification (0.2 V max. voltage drop at nominal current) it rather looks like 8 mA. Unfortunately I have no Cyclone V board at hand and can't check if lvcmos_d2 I/O standard is setting current strength that high or if it's only an IBIS file error.

I can tell that e.g. Cyclone 10LP has consistent current strength settings and IBIS files.

In contrast, the relation of Cyclone V lvcmos30 and lvttl30 I/V curves looks consistent. See below a visualization.

Best regards
Frank  

[RyusukeYOKOYA]

Hi Frank,

Thank you very much for taking the time to review the details and for providing additional insights.

I also find it difficult to determine whether this behavior is part of the intended specification or simply an error in the IBIS file. Given the ambiguity, I would appreciate it if an Intel employee could help clarify this point.

Thanks again for your support.

Best regards,
Ryusuke YOKOYA

[FvM]

Hi,
I got hold of an old Cyclone V based PCA and was able to measure drive strength of lvcmos 3.3V output. I found that is nearer to lvttl_d4 than lvttl_d16, in other words, just what we would expect for lvcmos_d2. Suggests that lvcmos_d2 spec in Cyclone V IBIS file is wrong and doesn't represent actual device behaviour.

Regards
Frank

[AqidAyman_Intel]

Hi,

I am checking this and waiting for confirmation from internal team. If I have any updates, I will share with you as soon as possible.

Regards,

Aqid

[AqidAyman_Intel]

Hello,

Based on my findings and discussion with internal team, the IBIS models below are expected to exhibit similar behaviour because, based on the HSPICE models for Cyclone V device, the bit settings for the 2mA current strength of 3.3 V LVCMOS and the 16mA current strength of 3.3 V LVTTL are the same. You can refer to the drive_select_IO.lib file located in the lib folder of the CV_GPIO_hspice_model_v2p0 for the bit settings for each drive strength setting.

lvcmos_rtpio_d2s1 and lvttl_rtpio_d16s1

lvcmos_rtpio_d2s1_p and lvttl_rtpio_d16s1_p

[RyusukeYOKOYA]

Dear Aqid,

Thank you very much for your continued support and for checking with the internal team.

I apologize in advance if my question seems a bit basic — I’m not very familiar with the detailed relationship between HSPICE and IBIS models, so I may be misunderstanding something fundamental.

To clarify your latest message:
You mentioned that the HSPICE models for 3.3V LVCMOS (2mA) and 3.3V LVTTL (16mA) use the same bit settings, and therefore the corresponding IBIS models are expected to behave similarly.

Could you please confirm whether this means:

• The HSPICE model is correct, and the IBIS models are also correct because they are based on that valid configuration?
  or
• The HSPICE model contains a mistake in the bit settings, and as a result, the IBIS models are also incorrect due to inheriting that issue?

I just want to make sure I understand whether the similarity in IBIS behavior is intentional and correct, or unintentional and due to an error in the underlying HSPICE model.

Additionally, I am planning to use the following I/O standards in my simulations:

• 3.3V LVCMOS (lvcmos_*)
• 3.3V LVTTL (lvttl_*)
• SSTL-135 (sstl135_*)
• Differential SSTL-135 (dsstl135_*)

Could you please advise which of these models are considered valid and reliable for signal integrity simulation purposes?

Thank you again for your patience and clarification.

Best regards,
Ryusuke YOKOYA

[FvM]

Hi,
latest post states that Cyclone V IBIS models are congruent with real hardware behaviour. I can confirm that LVTTL_16mA and LVCMOS_2mA I/O-standards have same output characteristic on tested Cyclone V device. I still don't understand why unusual high drive strength was selected for "LVCMOS_2mA" in contrast to 3.0V LVCMOS, but it's confirming with device models and in so far consistent. I expect that models for other I/O-standards are correct as well.
Regards
Frank

[AqidAyman_Intel]

I have also confirmed with the internal team that they have extracted the respective IBIS models through the Quartus IBIS Writer, which is the golden source. The models’ data from Quartus are the same as those from the external web, where the LVTTL 16mA is equivalent to the LVCMOS 2mA. Hence, I would say that the IBIS models and HSPICE models on the web match the golden source.

They have also run simulations to compare the signals across different current strength settings for LVTTL. From the simulation result, we can see that the signals across different current strength settings behave correctly. However, 3.3 V LVCMOS supports only one current strength setting (2mA), so we cannot perform the same comparison.

Anyway, they have also run IV simulations using HSPICE and confirmed that both LVTTL and LVCMOS can meet their respective current strength settings, where the current measured at VOH is higher than the configured current strength setting.