I've done some testing in SSN and found that simply having a no connect or tri-stated pin to separate aggressors from a victim pin, will reduce ground bounce the same amount as having programmable grounds. Proximity of aggressors to victims is the biggest contribute to SSN for FPGAs, so separating the sea of aggressors in a bus is a good design practice.
The no connect pins have no functionality since they are not connected internally to the die so by tying the N/C pins to VCC or GND this will not help with ground bounce.
True, true. In the tests we attempted, the pin locations that were tri-stated actually bonded to pads on the die which dispursed the SSOs at the the pad level. A no connect doesn't have any pad connection and thus probably won't help reduce SSN. The point of my post was that we found SSO is reduced by either a tri-stated pin next to the aggressors or a programmable GND. No real difference, at least on Stratix II.