The documentation doesn't explicitly say it (or if it does, I can't find it), but must the source for the reference clock for the C V's Transceiver Native PHY receiver come from the REFCLK0 pin pair, or can it be sourced from inside the FPGA?
Well, the C5 Transceiver handbook says that the transceivers can be clocked by a fractional-PLL (in integer mode), but the fitter seems to choose the fPLL's _input_ as the clock, not the fPLL clock output I explicitly coded ...
