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Referent Clock PCIe

Honored Contributor II

Hi guys 



I'd like if you can help my about PCIe pins connector. 



I have to communicate by PCIe two FPGAs, so I have to build a PCB like "Mother Board" where my FPGAs will communicate. 

My PCB will has a two PCIe female connector in orden to establish PCIe communication. I've searched by internet and I noticed that there are a differential pins called REFCLK.  

Some websites I've watched that they use REFCLK and another don't, but they don't tell nothing about REFCLK pins, so I'd like someone can help in orden to don't make mistake when make my PCB. 



My question is: 

If I connect one FPGA to another FPGA by PCIe, Must I ALWAYS use pins REFCLK or not??? 

I've searched by internet and I always find about lanes Rx and Tx, but I haven't found a good information about REFCLK. 



My another question is: 

if one FPGA is root- port and another is endpoint.....REFCLK is established by root-port or not ?? 



Thanks for your replys. 

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