SDRAM on DE0-nano board

[Altera_Forum]

Hi, 

 I am still not having any success writing and reading from the SDRAM on on the DE0-nano board from the FPGA. I have built a system in qsys which includes a Nios II and SDRAM controller and downloaded it to the board. The next thing I would like to do is write some code in VHDL or some program for the NIOS that reads and writes to the SDRAM.  How exactly does one achieve this? I believe the SDRAM controller takes care of all the control signals etc. so in order to write to it, I must specify the address in RAM first or just write data to the data pins connecting to it?  I am having problems understanding how this works. If anyone has more experience with this, I would appreciate your help.  Many thanks, Paul

[Altera_Forum]

Hi Dave, 

 From the you attached for the sdram controller in DE0 Nano, I can see that you instantiated ADC (analog digital converter) in the top level entity, however I could not find the vhdl file for ADC processing, do you mind to send me the ADC file?  I tried to understand how to create Qsys custom component for ADC Controller from Altera document (Using DE0 Nano ADC COntroller), too bad that those files are written in Verilog and I have difficulty to apply to my VHDL system, I also have sent a service request to Altera team but they do not have vhdl files for this, appreciate your help,   Thank you

[Altera_Forum]

--- Quote Start ---   From the you attached for the sdram controller in DE0 Nano, I can see that you instantiated ADC (analog digital converter) in the top level entity, however I could not find the vhdl file for ADC processing, do you mind to send me the ADC file?   --- Quote End ---   Look at the top-level code again - there is no ADC component instantiated.    --- Quote Start ---   I tried to understand how to create Qsys custom component for ADC Controller from Altera document (Using DE0 Nano ADC COntroller), too bad that those files are written in Verilog and I have difficulty to apply to my VHDL system, I also have sent a service request to Altera team but they do not have vhdl files for this, appreciate your help,    --- Quote End ---   I have not used the ADC on the DE0-nano. Its an SPI device, so its pretty easy to write a controller from scratch.   The type of controller you write depends on what you want to do with it, for example,  1. Use an existing "SPI Master Controller" and write software to interface to the ADC.  2. Create an Avalon-MM slave with 8 addresses, and when you access any one of these 8 addresses perform a conversion. Use a DMA controller to transfer blocks of samples to SDRAM.  3. Create an Avalon-MM ADC controller interface, where you set the ADC clock frequency, and the rate at which it auto-reads channels. Software then just reads the last conversion value from 8 registers.  Cheers, Dave

[Altera_Forum]

--- Quote Start ---  Look at the top-level code again - there is no ADC component instantiated.   I have not used the ADC on the DE0-nano. Its an SPI device, so its pretty easy to write a controller from scratch.   The type of controller you write depends on what you want to do with it, for example,  1. Use an existing "SPI Master Controller" and write software to interface to the ADC.  2. Create an Avalon-MM slave with 8 addresses, and when you access any one of these 8 addresses perform a conversion. Use a DMA controller to transfer blocks of samples to SDRAM.  3. Create an Avalon-MM ADC controller interface, where you set the ADC clock frequency, and the rate at which it auto-reads channels. Software then just reads the last conversion value from 8 registers.  Cheers, Dave  --- Quote End ---    Hi Dave, thanks a lot for your reply, I would have a look on the three options you stated here and see what I should do next, thanks again for your inputs!