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Hello Eevryone !
I have to implement some blocks of Simulink in System Gernator, so that i can get finally vhdl code after compilation and then i can put into FPGA. I have never used system generator before. Can anyone guide me how to do this. I may share my blocks in simulink as well. Hope someone can help me. Thanks :)Link Copied
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You'd better ask that question to a Xilinx forum.
This forum is about Altera devices.- Mark as New
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thanks but i am new to this forum as well,
which one is xilinx forum?- Mark as New
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:confused:

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