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Valued Contributor III
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SPI with generated clock output constraint problem

[list=1]  

[*]This interface is similar to SPI - runs with 10 MHz clock  

[*] I got 20 MHz reference clock in my design REF_CLK Data to transfer is shifted on falling edge on every 2nd toggle of REF_CLK clock to output port D  

[*] Output clock is generated by DFF {REF_CLK} [cant by generated by pll] and is transfered to output port C  

[*] Ts /Th of extrernal device is 8 ns  

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in sdc i got:  

[list=2]  

[*] create_clock -name REF_CLK -period 50.000 [get_ports {REF_CLK}]  

[*]create_generated_clock -name C -source [get_ports {REF_CLK}] -divide_by 2 [get_ports {C}]  

[*] set_output_delay -clock C 8 [get_ports {D}]  

[*] it doesnt work ;l  

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Valued Contributor III
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