I have a question regarding SSRAM timing. I want to calculate the appropriate phase between SSRAM controller's clock and SSRAM clock. I saw Altera's document about interfacing Cypress CY7C1380C (it's located in the quartus folder: C:\altera\91\quartus\sopc_builder\documents\ssram_interface_readme.html). In this document, there is a table with the column "Desired Tco (Avalon to SSRAM clock)" which includes the results of the detailed calculations to follow, and the column "Suggested PLL phase shift to SSRAM clock". What are the calculations for the values of "Suggested PLL phase shift to SSRAM"? Thanks!