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Valued Contributor III
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automatic slave module generation

I have written a lot of slave IP lately, and have developed somewhat of a template/style that I use. Sort of like Altera's template, but much cleaner, in my opinion. 

 

While having well-established methods of accomplishing what I need, it is still so much of a manual process, it is prone to errors and various compiler errors, such as missing semi-colons, mis-matched begin/end, etc. 

 

Other sources of errors: 

 

1) The register name may need to be entered in multiple places in the code, and you make a typo. 

 

2) The readdata assignment isn't mapped to the same addresses as the write logic. 

 

3) Support signals related to the register name, should be named similarly to the register name, and if you change the register's name, these all need chaging as well.  

 

In addition to that, I manually comment the memory map, so if it changes, the documentation needs changes. Sometimes the documentation doesn't get updated. 

 

I have a standard way of handing stuff such as: 

1) The register at a particular address using a single register name for a general read/write register. 

2) The register at a particular address using a single register name as a read-only, or write-only register 

3) The register at a particular address using different names for the read-only access, and write-only access. 

4) The register contains bitfields that are named. 

5) A write to a specific register address needs to trigger a pulse. The pulse may be used for anything such as a write request to a fifo, or a signal to another module to start it's state machine processing. 

6) A read to a specific register address needs to trigger a pulse. The pulse may be used as read acknowledge to a FIFO, or whatever else you might want. 

7) Writeable self-clearing bits in write-register. 

😎 Always 0 or 1 bits in read or write registers. 

 

I'm thinking of making a VB program to handle the generation of the source code, as a large register map require a lot of manual coding. Although it is somewhat mindless and robotically mechanical for me at this point, it is still time-consuming for prettying up the documentation and prone to making simple mistakes. 

 

A lot of my work requires replicating the functionality of a particular peripherial that already exists and has a well-defined datasheet and behavior. 

 

This leads me to believe I can make a program to enter in the registers, bitfields and required behaviors directly from a datasheet, and generate all the code that handles the CPU interface read/write, the other required behaviors, and documentation of the memory map in comments. 

 

Furthermore, I believe the custom user code can be placed in defined sections outside the generated code, so if anything changed you could regenerate the code. For example, if you are making your own custom peripherial, and need to add another register, this might expand the bits needed in your address range. This now changes not only the address definition, but also the case statement for the address when a write is occurring, the values compared to in the case statement, the readdata assignment logic, and any other code which compares the bit-range of the address register. Also, as development matures, I find myself changing the names of registers and bitfields to something more meaningful, or re-arranging the memory map to group similar register together. Changing a register name requires changing all other signal names responsible for additional behavior just for consistency. 

 

I think an app to enter in the register field names, bits, and behaviors (and allow you to save the configuration for later modification), would go a long way to solving these issues of the tedious, non-creative CPU interface code. This would allow me to get straight to work on the coding of the real "guts" module to be instantiated inside the auto-generated IP. 

 

Any comments, or additional basic features you can think of?
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Valued Contributor III
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Re: automatic slave module generation

I think register mapping is something that has been around for years, an no one has come up with a good solution to make it less tedious yet. I think we'll still be slogging away writing tedious code in 10 years time.

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Valued Contributor III
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Re: automatic slave module generation

Please tell me (and others) that you are being sarcastic. Your reputation is pretty high on this board. If not, I will have to prove you wrong. 🙂 

 

I happen to think this is an extremely straight-forward process based upon the coding structure I currently use. 

 

IP core development isn't nearly as difficult as the IP vendors would lead you to believe. 

 

It is just that there are so many ways to do the same thing, that some ways become problematic if you choose the wrong path. Just like writing a program in C, you can either make it ugly and unreadable, or structured, easily read, debugged and maintained.
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Valued Contributor III
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Re: automatic slave module generation

that sounds like a cool project 

 

i'm not stuck with this particular tedious task, but i have been thinking of writing applications for others. for example, Quartus can't generate an example instantiation with System Verilog multi-dimensional ports which leaves me with wasting time doing it manually 

 

my idea was to create a web-based application where you paste in the module declaration and get an instantiation, including multi-dimensional ports. it could also be more flexible than Quartus, for example you could customize the signal name (append _sig, _v, nothing) 

 

anyhow, my 2 cents is to make it a web application. i'd be interested in collaborating to build a suite of tools to cut out tedious work
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Valued Contributor III
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Re: automatic slave module generation

I agree that a web interface would be a nice the way to go, but I don't do web pages, nor want to learn, so that might be something you'd be able to help me on. 

 

For changes, you'd need the original configuration file and source code to read in. I'm not sure how you'd do that with a web based design, but I'm sure there's some way to make it work, like uploading the original configuration/source file and downloading the new configuration file/source file. 

 

I'm just going to proceed with VB for the time being, and I'll post some screen shots of the interface and sample output here to get more feedback. 

 

I'd like to see some $$ from this, but think the best thing would be to release it for free and hope some more work will come my way because of it.
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Valued Contributor III
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Re: automatic slave module generation

Here are the screen shots of my VB program I created, and the sample output of what it generated. The signals are representative of an I2C IP core. 

 

I have expanded the scope considerably, as I think the whole thing can be generated, if you tell it the module that accepts your write register values, and returns the read register values. 

 

There are still more things to do, especially validation of the parameters, signals directions and widths into and out of other instantiated modules, etc. but most of the basic things I originally intended on implementing are working. 

 

As it stands now, without validation, you can configure things in such a way that will cause problems.
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Valued Contributor III
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Re: automatic slave module generation

Here is the auto-generated verilog file.

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