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Valued Contributor III
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FIFO output BigEndian or LittleEndian!

hi,when using FIFO of LPM,output width is made different from input width,if I make input[63:0] and output[7:0],the waveform shows that the output starts from the LSB of the input ,ie,[7:0]、[15:8]、[23:16]...so,how can I make it starts from the MSB of the input?

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Valued Contributor III
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Re: FIFO output BigEndian or LittleEndian!

Swap the byte-order at the input to the FIFO. 

 

Regards, 

 

Thomas
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Valued Contributor III
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Re: FIFO output BigEndian or LittleEndian!

hi!So u mean that change the source data sequence at the input port first?If don't,there is no way?But I think that it will that a clk cycle...

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Valued Contributor III
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Re: FIFO output BigEndian or LittleEndian!

The FIFO is little endian so if you want the output to be big endian then like tentner said reverse the byte lanes of the input before the data enters the FIFO. This is just wires and will not affect the timing or latency at all. 

 

So if your 64 bit input to the FIFO was called "data" and you want to reverse the data just do something like this (in verilog) and pass "reversed_data" to the input of the FIFO instead: 

 

assign reversed_data = {data[7:0], data[15:8], ...... ,data[55:48], data[63:56]};
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Valued Contributor III
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Re: FIFO output BigEndian or LittleEndian!

 

--- Quote Start ---  

The FIFO is little endian so if you want the output to be big endian then like tentner said reverse the byte lanes of the input before the data enters the FIFO. This is just wires and will not affect the timing or latency at all. 

 

So if your 64 bit input to the FIFO was called "data" and you want to reverse the data just do something like this (in verilog) and pass "reversed_data" to the input of the FIFO instead: 

 

assign reversed_data = {data[7:0], data[15:8], ...... ,data[55:48], data[63:56]}; 

--- Quote End ---  

 

 

 

I think I got your brilliant idea!Indeed,it is!Thank U so much!
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Valued Contributor III
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Re: FIFO output BigEndian or LittleEndian!

The answer is somewhat more complex: the swapping depends on what your 64 bits at the input represent. For a 64 bit packet representing 8 bytes in little-endian we basically have 4 choices in big-endian format:  

8 bit words -> the byte order remains -> b0 b1 b2 b3 b4 b5 b6 b7 

16 bit words -> swap/reverse every pair -> b1 b0 b3 b2 b5 b4 b7 b6 

32 bit words -> swap/reverse every quad -> b3 b2 b1 b0 b7 b6 b5 b4 

64 bit words -> reverse all 8 -> b7 b6 b5 b4 b3 b2 b1 b0
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Valued Contributor III
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Re: FIFO output BigEndian or LittleEndian!

 

--- Quote Start ---  

The answer is somewhat more complex: the swapping depends on what your 64 bits at the input represent. For a 64 bit packet representing 8 bytes in little-endian we basically have 4 choices in big-endian format: 

 

8 bit words -> the byte order remains -> b0 b1 b2 b3 b4 b5 b6 b7 

16 bit words -> swap/reverse every pair -> b1 b0 b3 b2 b5 b4 b7 b6 

32 bit words -> swap/reverse every quad -> b3 b2 b1 b0 b7 b6 b5 b4 

64 bit words -> reverse all 8 -> b7 b6 b5 b4 b3 b2 b1 b0 

 

--- Quote End ---  

you are right.Actrually,It's 64 bit words in this case.You just reminded me other cases that I've not noticed.In my case,I need input [63:0]data to the FIFO,and read out as the sequence of [63:56]、[55:48].....[7:0].So I must reverse all bytes at the input port first.
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