Same PLL clock domain crossing

[Altera_Forum]

I have two clock outputs from one PLL. One clock is 80Mhz and the other is 40Mhz. 

Valid and data signals from the 100Mhz are long enough in time to be seen in the 40Mhz domain. My question is, should I add special timing constraints in an SDC file for this type of clk domain crossing?  Thanks

[Altera_Forum]

--- Quote Start ---  ... signals from the 100Mhz are long enough ...  --- Quote End ---   I guess you meant 80MHz here. In this case no special constraints are required, since the clocks have a simple setup/hold relationship. You possibly may want to add multicycles if you don't need the strict default relationship

[Altera_Forum]

Sorry I meant the 80Mhz 

Thank you. The main purpose for this is that I want to take one data from the fast domain, drop the next, and so on. Take one and leave one.

[Altera_Forum]

In fact you indeed _need_ constraints, but the good news is that you get the constraints you need by simply using the Altera extension to SDC "derive_pll_clocks". 

Make sure you do not place the two clocks in different clock groups nor cut the timing paths. Timequest will report the clock to clock transfers.

[Altera_Forum]

--- Quote Start ---  In fact you indeed _need_ constraints, but the good news is that you get the constraints you need by simply using the Altera extension to SDC "derive_pll_clocks". Make sure you do not place the two clocks in different clock groups nor cut the timing paths. Timequest will report the clock to clock transfers.  --- Quote End ---    OK I use derive_pll_clocks as you suggest. The design is very simple so I don't use clock groups.  Thanks