Scaling core clock of 100MHz to 23MHz & 20MHz

[Altera_Forum]

Hello All, 

 I am using Altera Stratix II for my project. I have generated a PLL in LVDs mode(for a deserialization factor of 10 and date rates is 1000Mbps). The two available clock sources on the board are 100MHz and 62.5MHz. I need to generate 23MHz and 20MHz MHz clocks for a module in my project.  When I try to generate a PLL in LVDs mode in Mega Core Wizard, by default it selects a FAST PLL and the minimum output frequency is 33.3333MHz.  Can I use any other logic and generate a 23MHz and 20MHz clock from 100MHz core clock. Can any one of you suggest a solution to this problem.  Many thanks in advance,

[Altera_Forum]

I don't know how you got a minimum output frequency of 33 MHz. I understand, that your LVDS units have data rate of 200/230 MHz or a slow clock of 20/23 Mhz respectively. By using the LVDS Megawizard, you see that the 200 MHz LVDS can operate from a 100 MHz inclock but the 230 MHz can't. It would need e. g. 23 or 115 MHz inclock. So you need cascaded PLLs, but they are available with Stratix II.

[Altera_Forum]

thku, date rates is 1000Mbps

[Altera_Forum]

Yes, I overlooked the 1000 MHz data rate. But then I didn't clearly understand how the 20 or 23 MHz clock is related to LVDS transmission? If it isnt'n at all, you can use a separate PLLs to generate the clocks.  

 A 20 MHz clock could be used as input or output frame clock for 100/1000 MHz LVDS channel (I don't see a similar purpose for a 23 MHz clock). But it can't be generated or received by the LVDS PLL directly, apparently due to restriction of available scale factors. So you have to use additional PLLs. Synchronisation shouldn't be an issue as long as the 100 MHz LVDS slow clock is the inclk for both PLLs.   For source synchronous reception with 20 MHz input clock, a 20/100 MHz PLL must be used in front of the LVDS receiver. Using DPA hopefully cancels all problems with additional delays.

[Altera_Forum]

Ya, I am using an Enhanced Pll to get a 23MHz clock with an input of 100MHz(Slow Clock from FPLL) It works. On the receiver end I am receiving the data, and with the same 23MHz clk i am storing the data into RAM.  

 I am sending a 10 bit constant value from Sender to Receiver but the thing is data sampling is not proper for example if i send :   Sender 01 0011 0101 Receiver 11 0101 0100 (RAM)  Sender 11 0011 0100 Receiver 10 1001 1001 (RAM)  I think I need some kind of data training patterns. Could you please suggest me so ideas?

[Altera_Forum]

I haven't been using Stratix II respectively Arria GX LVDS receiver without DPA and word alignment, so I'm not sure about the initial inclk to data alignment. But it seems, as it has a built-in slowclock phase shift. The results are not as expected with the word boundary aligned to inclk rising edge.  

 The disadvantage with DPA and data realignment is the need to coordinate train pattern send time (and some additional design complexity). Your test data would be e. g. suited as train pattern. After DPA reset, first step is adjustment of bit phase by DPA. With usual binary data, the DPA circuitry must be disabled in normal operation, cause no edges are present in case of all zero or all one data. During word alignment step, the channel alignment input is pulsed until the train pattern matches.  If your application has stable LVDS data phase and executing a train phase is unsuitable, then you can adjust the phase manually. An adjustment beyond a bit time duration can be achieved with an external PLL. Alternatively, the channel alignment input could be used to shift the data by a fixed number of bits and the 360° inclk adjustment can center the bit sampling to input data.

[Altera_Forum]

Thanku. Ya I am using a DPA block and an external PLL(in LVDS mode). The slow clock is phaseshifter with the input clock by 4.5deg and Serial clock at data rate by 45deg respectively. I am completly new to this DPA. Can i know, whether the data alignment is possible without using a training patern or the otherway arroung could u please tell me what acctually u ment by  

 "If your application has stable LVDS data phase and executing a train phase is unsuitable, then you can adjust the phase manually. An adjustment beyond a bit time duration can be achieved with an external PLL. Alternatively, the channel alignment input could be used to shift the data by a fixed number of bits and the 360° inclk adjustment can center the bit sampling to input data."  reg sa

[Altera_Forum]

Using the DPA block without a train pattern may cause problems in some cases, I think. 

- During DPA calibration time (when rx_dpll_hold[] is deasserted), the input stream must be assured to have edges for bit phase alignment. - Depending on the initial phase, DPA calibration may shift the word alignment by one bit, possibly different for multiple channels.  So I think, the receiver should be operated either with DPA enabled and word realignment (CDA) utilizing a train pattern or with fixed phase. If other users see a meaningful application for DPA without CDA and a train pattern, I'm interested to learn about.  An application with fixed clock to data skew (e.g. onboard wiring) should be basically able to work without DPA and CDA. If you are already using an external PLL, you should be able to adjust slow and fast clock phases empirically to achieve correct alignment.   Shifting both clocks by the same amount is identical to modifying INCLOCK_DATA_ALIGNMENT of an LVDS internal PLL. The available increment is 1/8 of bit duration. You can evaluate at which phase the alignment is advancing one bit and then shift the clocks 180° to center alignment. Then the slow clock can be shifted by full bit clock intervalls to achieve the correct word alignment. A negative shift is also possible.  A special point is, that CDA must not allowed to shift across a word boundary in multiple channel transmission. This may happen, if the initial phase (after CDA reset) is near to correct alignment and a negative shift would be needed for some channels.

[Altera_Forum]

Thanku. Ya! I think i need some kind of training pattern. Do u have any documents (pdf or so) related to this issue i mean how to train a DPA.

[Altera_Forum]

If I rember right, I found all necessary information in the alt_lvds Megafunction user manual. Some reference designs are also available from Altera website, but I'm not sure if they include the DPA/CDA train logic.

[Altera_Forum]

hi after a long time sry was busy with some other work :( 

 I have gone through that document. It is given that using "rx_channel_data_align" one can insert bit latency into the serial data. I have tried for different bit insertions in Megacore but there is no change in the word alignment. Do u have any idea how to use this "rx_channel_data_align" input port such that the word alignment is effected?

[Altera_Forum]

Hi, 

 The document is not clearly explaining how to use Data Realignment Circutry inorder to align the word boandry. There is no change if in the word boundary when i change the programmable bit rollover point(1 to 11 bit-times).   Do u know how to introduce a pulse to the "rx_channel_data_align" input port   reg sa

[Altera_Forum]

Hi, 

 The document is not clearly explaining how to use Data Realignment Circutry inorder to align the word boandry. There is no change if in the word boundary when i change the programmable bit rollover point(1 to 11 bit-times).  Do u know how to introduce a pulse to the "rx_channel_data_align" input port  reg sa

[Altera_Forum]

Yes, the "rollover point" or rx_cda_max constant apparently doesn't affect the initial cda position. The position is advanced by pulsing rx_channel_data_align. I'm using a state machine clocked with DESER slow clock (rx_outclock) to operate the cda logic, so i get pulses one rx_outclock in width. After a applying a pulse, you have to wait for the delay change to propagate through DESER until the new phase is visible at the output.

[Altera_Forum]

Ohh is it. I am not using any statemachine, is this state machine also a part of Megacore or ? 

I dint enable rx_outclock port, should i enable it in Megacore. If possible could u please send that state machine program to me?  Can i check this in ModelSim too. I mean the behaviour of DPA block.  Reg sa

[Altera_Forum]

do u mean "rx_outclock port" u are using is the slow clk from External Pll or??? because I am using LVDS in External Pll mode. I dont have rx-outclock.

[Altera_Forum]

It's not part of the MegaCore, it's a user design. If I remember right, there have been also Altera design examples with DPA, but I don't remember where I had seen them. 

 It's not particularly necessary to enable rx_outclock, but I wonder which clock you are using to process your received data.   I give you my code as is. It's for a 4x4 multichannel LVDS revceiver. As an additional hint, the dpa_reset[1:4] signal is used as start trigger for train sequence, it is generated by another design component communicating with LVDS sender.  4'h3 is the respective train pattern.   always @ (posedge RESET or posedge rx_outclock_sig) begin if (RESET) begin train_timer <= 8'hff; train <= 0; rx_dpa_locked_v <= 0; ModulFehler <= 4'hf; end else begin if (dpa_reset) begin train_timer <= 0; train <= dpa_reset; rx_dpa_locked_v <= 0; end else begin case (train_timer) 255: begin train <= 0; rx_channel_data_align_sig <= 0; for (N=1;N<=4;N=N+1) if (train) begin ModulFehler = 0; for (M=8*N-8;M<8*N;M=M+1) if (!rx_dpa_locked_sig || rx_cda_max_sig) begin ModulFehler = 1; end end end default: begin for (N=1;N<=4;N=N+1) for (M=8*N-8;M<8*N;M=M+1) if (train) begin if ((train_timer % 8) == 7 && rx_dpa_locked_sig) rx_dpa_locked_v <= 1; if ((train_timer % 8) == 7 && rx_dpa_locked_v && !rx_cda_max_sig && {rx_out_sig_i,rx_out_sig_i, rx_out_sig_i,rx_out_sig_i} != 4'h3) rx_channel_data_align_sig <= 1; else rx_channel_data_align_sig <= 0; end train_timer <= train_timer + 1; end endcase end end for (N=1;N<=4;N=N+1) for (M=8*N-8;M<8*N;M=M+1) begin rx_cda_reset_sig = dpa_reset; rx_reset_sig = dpa_reset; rx_dpll_hold_sig = !train; end end

[Altera_Forum]

Thku.. i shall try to analyse it. Well I am currently using slow clk of 100MHz on the receiver side User application. For serial transmission i am using 1000MHz clk. Boz i am using a deserilization factor of 10.

[Altera_Forum]

cant really understand :(.

[Altera_Forum]

Yes, the DPA control should use 100 MHz (or slower) in this case.  

 I just was aware, that my design is actually 4 modules x 8 LVDS channels x 4 bit deserialization factor. The train can be done separately for each of the 4 modules, DPA control within a train sequence is also separate for each LVDS channel. You should analyze the logic for one channel first, it's much more simple of course. The important thing is to assure, that the sender is actually transmitting the train pattern while DPA train is activated (for 256 clocks in my design).

[Altera_Forum]

Does the DPA block behave the same in ModelSim, I mean i have introduced a transportation delay in my system and now i am trying to adjust DPA block and want to check how it actually behaves. I shall try to implement some statemachine concept as suggested by you. But, would it be possible for me to notice the chages in ModelSim before going on to the real hardware?